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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
Use movlps / movhps to modify low / high half of 16-byet memory location.
llvm-svn: 51501
This commit is contained in:
Evan Cheng
parent
2412469191
commit
4f660778f0
@ -505,46 +505,6 @@ nodes which are selected to max / min instructions that are marked commutable.
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//===---------------------------------------------------------------------===//
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We should compile this:
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#include <xmmintrin.h>
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typedef union {
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int i[4];
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float f[4];
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__m128 v;
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} vector4_t;
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void swizzle (const void *a, vector4_t * b, vector4_t * c) {
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b->v = _mm_loadl_pi (b->v, (__m64 *) a);
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c->v = _mm_loadl_pi (c->v, ((__m64 *) a) + 1);
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}
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to:
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_swizzle:
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movl 4(%esp), %eax
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movl 8(%esp), %edx
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movl 12(%esp), %ecx
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movlps (%eax), %xmm0
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movlps %xmm0, (%edx)
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movlps 8(%eax), %xmm0
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movlps %xmm0, (%ecx)
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ret
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not:
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swizzle:
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movl 8(%esp), %eax
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movaps (%eax), %xmm0
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movl 4(%esp), %ecx
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movlps (%ecx), %xmm0
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movaps %xmm0, (%eax)
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movl 12(%esp), %eax
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movaps (%eax), %xmm0
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movlps 8(%ecx), %xmm0
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movaps %xmm0, (%eax)
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ret
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//===---------------------------------------------------------------------===//
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We should materialize vector constants like "all ones" and "signbit" with
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code like:
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@ -363,6 +363,32 @@ static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load,
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Store.getOperand(2), Store.getOperand(3));
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}
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/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
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///
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static bool isRMWLoad(SDOperand N, SDOperand Chain, SDOperand Address,
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SDOperand &Load) {
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if (N.getOpcode() == ISD::BIT_CONVERT)
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N = N.getOperand(0);
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LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
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if (!LD || LD->isVolatile())
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return false;
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if (LD->getAddressingMode() != ISD::UNINDEXED)
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return false;
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
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return false;
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if (N.hasOneUse() &&
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N.getOperand(1) == Address &&
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N.Val->isOperandOf(Chain.Val)) {
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Load = N;
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return true;
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}
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return false;
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}
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/// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
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/// This is only run if not in -fast mode (aka -O0).
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/// This allows the instruction selector to pick more read-modify-write
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@ -414,8 +440,8 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
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SDOperand N1 = I->getOperand(1);
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SDOperand N2 = I->getOperand(2);
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if (MVT::isFloatingPoint(N1.getValueType()) ||
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MVT::isVector(N1.getValueType()) ||
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if ((MVT::isFloatingPoint(N1.getValueType()) &&
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!MVT::isVector(N1.getValueType())) ||
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!N1.hasOneUse())
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continue;
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@ -429,20 +455,13 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADDC:
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case ISD::ADDE: {
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case ISD::ADDE:
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case ISD::VECTOR_SHUFFLE: {
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SDOperand N10 = N1.getOperand(0);
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SDOperand N11 = N1.getOperand(1);
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if (ISD::isNON_EXTLoad(N10.Val))
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RModW = true;
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else if (ISD::isNON_EXTLoad(N11.Val)) {
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RModW = true;
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std::swap(N10, N11);
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}
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RModW = RModW && N10.Val->isOperandOf(Chain.Val) && N10.hasOneUse() &&
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(N10.getOperand(1) == N2) &&
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(N10.Val->getValueType(0) == N1.getValueType());
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if (RModW)
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Load = N10;
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RModW = isRMWLoad(N10, Chain, N2, Load);
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if (!RModW)
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RModW = isRMWLoad(N11, Chain, N2, Load);
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break;
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}
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case ISD::SUB:
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@ -456,12 +475,7 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
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case X86ISD::SHLD:
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case X86ISD::SHRD: {
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SDOperand N10 = N1.getOperand(0);
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if (ISD::isNON_EXTLoad(N10.Val))
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RModW = N10.Val->isOperandOf(Chain.Val) && N10.hasOneUse() &&
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(N10.getOperand(1) == N2) &&
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(N10.Val->getValueType(0) == N1.getValueType());
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if (RModW)
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Load = N10;
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RModW = isRMWLoad(N10, Chain, N2, Load);
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break;
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}
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}
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@ -2977,13 +2977,15 @@ def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
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MOVHP_shuffle_mask)),
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(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
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def : Pat<(v4i32 (vector_shuffle VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)),
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MOVLP_shuffle_mask)),
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(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
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MOVLP_shuffle_mask)),
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(MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
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def : Pat<(v4i32 (vector_shuffle VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)),
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MOVHP_shuffle_mask)),
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(MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
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@ -2991,6 +2993,37 @@ def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
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(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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}
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// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
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// (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
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def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
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MOVLP_shuffle_mask)), addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
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MOVLP_shuffle_mask)), addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
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MOVHP_shuffle_mask)), addr:$src1),
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(MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
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MOVHP_shuffle_mask)), addr:$src1),
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(MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(store (v4i32 (vector_shuffle
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(bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
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MOVLP_shuffle_mask)), addr:$src1),
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(MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
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MOVLP_shuffle_mask)), addr:$src1),
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(MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(store (v4i32 (vector_shuffle
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(bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
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MOVHP_shuffle_mask)), addr:$src1),
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(MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
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MOVHP_shuffle_mask)), addr:$src1),
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(MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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let AddedComplexity = 15 in {
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// Setting the lowest element in the vector.
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def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
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25
test/CodeGen/X86/vec_shuffle-18.ll
Normal file
25
test/CodeGen/X86/vec_shuffle-18.ll
Normal file
@ -0,0 +1,25 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep mov | count 7
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%struct.vector4_t = type { <4 x float> }
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define void @swizzle(i8* %a, %struct.vector4_t* %b, %struct.vector4_t* %c) nounwind {
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entry:
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%tmp9 = getelementptr %struct.vector4_t* %b, i32 0, i32 0 ; <<4 x float>*> [#uses=2]
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%tmp10 = load <4 x float>* %tmp9, align 16 ; <<4 x float>> [#uses=1]
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%tmp14 = bitcast i8* %a to double* ; <double*> [#uses=1]
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%tmp15 = load double* %tmp14 ; <double> [#uses=1]
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%tmp16 = insertelement <2 x double> undef, double %tmp15, i32 0 ; <<2 x double>> [#uses=1]
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%tmp18 = bitcast <2 x double> %tmp16 to <4 x float> ; <<4 x float>> [#uses=1]
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%tmp19 = shufflevector <4 x float> %tmp10, <4 x float> %tmp18, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp19, <4 x float>* %tmp9, align 16
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%tmp28 = getelementptr %struct.vector4_t* %c, i32 0, i32 0 ; <<4 x float>*> [#uses=2]
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%tmp29 = load <4 x float>* %tmp28, align 16 ; <<4 x float>> [#uses=1]
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%tmp26 = getelementptr i8* %a, i32 8 ; <i8*> [#uses=1]
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%tmp33 = bitcast i8* %tmp26 to double* ; <double*> [#uses=1]
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%tmp34 = load double* %tmp33 ; <double> [#uses=1]
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%tmp35 = insertelement <2 x double> undef, double %tmp34, i32 0 ; <<2 x double>> [#uses=1]
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%tmp37 = bitcast <2 x double> %tmp35 to <4 x float> ; <<4 x float>> [#uses=1]
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%tmp38 = shufflevector <4 x float> %tmp29, <4 x float> %tmp37, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp38, <4 x float>* %tmp28, align 16
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ret void
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}
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