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[X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single regular expressions in scheduler models.

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llvm-svn: 327816
This commit is contained in:
Craig Topper 2018-03-19 00:56:11 +00:00
parent 4c5fcacceb
commit 4f746e48d4
2 changed files with 8 additions and 16 deletions
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12
lib/Target/X86/X86SchedHaswell.td
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@ -1608,14 +1608,10 @@ def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> {
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[HWWriteResGroup15], (instregex "RORX32mi")>;
def: InstRW<[HWWriteResGroup15], (instregex "RORX64mi")>;
def: InstRW<[HWWriteResGroup15], (instregex "SARX32rm")>;
def: InstRW<[HWWriteResGroup15], (instregex "SARX64rm")>;
def: InstRW<[HWWriteResGroup15], (instregex "SHLX32rm")>;
def: InstRW<[HWWriteResGroup15], (instregex "SHLX64rm")>;
def: InstRW<[HWWriteResGroup15], (instregex "SHRX32rm")>;
def: InstRW<[HWWriteResGroup15], (instregex "SHRX64rm")>;
def: InstRW<[HWWriteResGroup15], (instregex "RORX(32|64)mi")>;
def: InstRW<[HWWriteResGroup15], (instregex "SARX(32|64)rm")>;
def: InstRW<[HWWriteResGroup15], (instregex "SHLX(32|64)rm")>;
def: InstRW<[HWWriteResGroup15], (instregex "SHRX(32|64)rm")>;
def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
let Latency = 6;

12
lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -1941,15 +1941,11 @@ def: InstRW<[SKLWriteResGroup74], (instregex "ADCX(32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "ADOX(32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[SKLWriteResGroup74], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "RORX32mi")>;
def: InstRW<[SKLWriteResGroup74], (instregex "RORX64mi")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SARX32rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SARX64rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "RORX(32|64)mi")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SARX(32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SBB(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHLX32rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHLX64rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHRX32rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHRX64rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHLX(32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHRX(32|64)rm")>;
def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
let Latency = 6;