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[NFC] Use [MC]Register in Live-ness tracking
Differential Revision: https://reviews.llvm.org/D90611
This commit is contained in:
Gaurav Jain
parent
6989bc45bd
commit
4f8e5f73dc
@ -114,8 +114,8 @@ class VirtRegMap;
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LiveInterval &getInterval(Register Reg) {
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if (hasInterval(Reg))
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return *VirtRegIntervals[Reg.id()];
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else
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return createAndComputeVirtRegInterval(Reg);
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return createAndComputeVirtRegInterval(Reg);
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}
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const LiveInterval &getInterval(Register Reg) const {
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@ -142,14 +142,14 @@ class VirtRegMap;
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}
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/// Interval removal.
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void removeInterval(unsigned Reg) {
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void removeInterval(Register Reg) {
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delete VirtRegIntervals[Reg];
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VirtRegIntervals[Reg] = nullptr;
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}
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/// Given a register and an instruction, adds a live segment from that
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/// instruction to the end of its MBB.
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LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
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LiveInterval::Segment addSegmentToEndOfBlock(Register Reg,
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MachineInstr &startInst);
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/// After removing some uses of a register, shrink its live range to just
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@ -167,7 +167,7 @@ class VirtRegMap;
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/// the lane mask of the subregister range.
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/// This may leave the subrange empty which needs to be cleaned up with
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/// LiveInterval::removeEmptySubranges() afterwards.
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void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
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void shrinkToUses(LiveInterval::SubRange &SR, Register Reg);
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/// Extend the live range \p LR to reach all points in \p Indices. The
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/// points in the \p Indices array must be jointly dominated by the union
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@ -463,7 +463,7 @@ class VirtRegMap;
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bool computeDeadValues(LiveInterval &LI,
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SmallVectorImpl<MachineInstr*> *dead);
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static LiveInterval* createInterval(unsigned Reg);
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static LiveInterval *createInterval(Register Reg);
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void printInstrs(raw_ostream &O) const;
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void dumpInstrs() const;
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@ -474,7 +474,7 @@ class VirtRegMap;
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using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo*>, 16>;
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void extendSegmentsToUses(LiveRange &Segments,
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ShrinkToUsesWorkList &WorkList, unsigned Reg,
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ShrinkToUsesWorkList &WorkList, Register Reg,
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LaneBitmask LaneMask);
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/// Helper function for repairIntervalsInRange(), walks backwards and
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@ -484,7 +484,7 @@ class VirtRegMap;
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void repairOldRegInRange(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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const SlotIndex endIdx, LiveRange &LR,
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unsigned Reg,
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Register Reg,
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LaneBitmask LaneMask = LaneBitmask::getAll());
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class HMEditor;
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@ -105,8 +105,7 @@ public:
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/// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
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/// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
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/// MBB, it is not considered live in.
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bool isLiveIn(const MachineBasicBlock &MBB,
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unsigned Reg,
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bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
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MachineRegisterInfo &MRI);
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void dump() const;
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@ -149,25 +148,25 @@ private: // Intermediate data structures
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/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
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/// uses. Pay special attention to the sub-register uses which may come below
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/// the last use of the whole register.
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bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
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bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
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/// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
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void HandleRegMask(const MachineOperand&);
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void HandlePhysRegUse(unsigned Reg, MachineInstr &MI);
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void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
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void HandlePhysRegUse(Register Reg, MachineInstr &MI);
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void HandlePhysRegDef(Register Reg, MachineInstr *MI,
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SmallVectorImpl<unsigned> &Defs);
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void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
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/// FindLastRefOrPartRef - Return the last reference or partial reference of
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/// the specified register.
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MachineInstr *FindLastRefOrPartRef(unsigned Reg);
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MachineInstr *FindLastRefOrPartRef(Register Reg);
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/// FindLastPartialDef - Return the last partial def of the specified
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/// register. Also returns the sub-registers that're defined by the
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/// instruction.
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MachineInstr *FindLastPartialDef(unsigned Reg,
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SmallSet<unsigned,4> &PartDefRegs);
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MachineInstr *FindLastPartialDef(Register Reg,
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SmallSet<unsigned, 4> &PartDefRegs);
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/// analyzePHINodes - Gather information about the PHI nodes in here. In
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/// particular, we want to map the variable information of a virtual
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@ -184,21 +183,21 @@ public:
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/// RegisterDefIsDead - Return true if the specified instruction defines the
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/// specified register, but that definition is dead.
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bool RegisterDefIsDead(MachineInstr &MI, unsigned Reg) const;
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bool RegisterDefIsDead(MachineInstr &MI, Register Reg) const;
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//===--------------------------------------------------------------------===//
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// API to update live variable information
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/// replaceKillInstruction - Update register kill info by replacing a kill
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/// instruction with a new one.
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void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
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void replaceKillInstruction(Register Reg, MachineInstr &OldMI,
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MachineInstr &NewMI);
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/// addVirtualRegisterKilled - Add information about the fact that the
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/// specified register is killed after being used by the specified
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/// instruction. If AddIfNotFound is true, add a implicit operand if it's
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/// not found.
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void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr &MI,
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void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI,
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bool AddIfNotFound = false) {
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if (MI.addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
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getVarInfo(IncomingReg).Kills.push_back(&MI);
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@ -208,14 +207,14 @@ public:
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/// register from the live variable information. Returns true if the
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/// variable was marked as killed by the specified instruction,
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/// false otherwise.
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bool removeVirtualRegisterKilled(unsigned reg, MachineInstr &MI) {
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if (!getVarInfo(reg).removeKill(MI))
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bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI) {
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if (!getVarInfo(Reg).removeKill(MI))
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return false;
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bool Removed = false;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
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if (MO.isReg() && MO.isKill() && MO.getReg() == Reg) {
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MO.setIsKill(false);
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Removed = true;
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break;
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@ -234,7 +233,7 @@ public:
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/// addVirtualRegisterDead - Add information about the fact that the specified
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/// register is dead after being used by the specified instruction. If
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/// AddIfNotFound is true, add a implicit operand if it's not found.
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void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr &MI,
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void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI,
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bool AddIfNotFound = false) {
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if (MI.addRegisterDead(IncomingReg, TRI, AddIfNotFound))
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getVarInfo(IncomingReg).Kills.push_back(&MI);
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@ -244,14 +243,14 @@ public:
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/// register from the live variable information. Returns true if the
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/// variable was marked dead at the specified instruction, false
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/// otherwise.
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bool removeVirtualRegisterDead(unsigned reg, MachineInstr &MI) {
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if (!getVarInfo(reg).removeKill(MI))
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bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI) {
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if (!getVarInfo(Reg).removeKill(MI))
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return false;
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bool Removed = false;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
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if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
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MO.setIsDead(false);
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Removed = true;
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break;
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@ -270,7 +269,7 @@ public:
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/// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
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/// register.
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VarInfo &getVarInfo(unsigned RegIdx);
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VarInfo &getVarInfo(Register Reg);
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void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
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MachineBasicBlock *BB);
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@ -278,17 +277,17 @@ public:
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MachineBasicBlock *BB,
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SmallVectorImpl<MachineBasicBlock *> &WorkList);
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void HandleVirtRegDef(unsigned reg, MachineInstr &MI);
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void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr &MI);
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void HandleVirtRegDef(Register reg, MachineInstr &MI);
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void HandleVirtRegUse(Register reg, MachineBasicBlock *MBB, MachineInstr &MI);
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bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) {
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bool isLiveIn(Register Reg, const MachineBasicBlock &MBB) {
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return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
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}
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/// isLiveOut - Determine if Reg is live out from MBB, when not considering
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/// PHI nodes. This means that Reg is either killed by a successor block or
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/// passed through one.
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bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB);
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bool isLiveOut(Register Reg, const MachineBasicBlock &MBB);
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/// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All
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/// variables that are live out of DomBB and live into SuccBB will be marked
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@ -304,10 +303,10 @@ public:
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std::vector<SparseBitVector<>> &LiveInSets);
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/// isPHIJoin - Return true if Reg is a phi join register.
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bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }
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bool isPHIJoin(Register Reg) { return PHIJoins.test(Reg.id()); }
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/// setPHIJoin - Mark Reg as a phi join register.
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void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
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void setPHIJoin(Register Reg) { PHIJoins.set(Reg.id()); }
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};
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} // End llvm namespace
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@ -159,7 +159,7 @@ void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
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// Dump the virtregs.
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = Register::index2VirtReg(i);
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Register Reg = Register::index2VirtReg(i);
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if (hasInterval(Reg))
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OS << getInterval(Reg) << '\n';
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}
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@ -183,7 +183,7 @@ LLVM_DUMP_METHOD void LiveIntervals::dumpInstrs() const {
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}
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#endif
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LiveInterval* LiveIntervals::createInterval(unsigned reg) {
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LiveInterval *LiveIntervals::createInterval(Register reg) {
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float Weight = Register::isPhysicalRegister(reg) ? huge_valf : 0.0F;
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return new LiveInterval(reg, Weight);
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}
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@ -199,7 +199,7 @@ bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
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void LiveIntervals::computeVirtRegs() {
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = Register::index2VirtReg(i);
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Register Reg = Register::index2VirtReg(i);
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if (MRI->reg_nodbg_empty(Reg))
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continue;
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LiveInterval &LI = createEmptyInterval(Reg);
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@ -286,7 +286,7 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
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bool IsRootReserved = true;
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for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
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Super.isValid(); ++Super) {
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unsigned Reg = *Super;
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MCRegister Reg = *Super;
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if (!MRI->reg_empty(Reg))
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LICalc->createDeadDefs(LR, Reg);
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// A register unit is considered reserved if all its roots and all their
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@ -305,7 +305,7 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
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for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
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for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
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Super.isValid(); ++Super) {
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unsigned Reg = *Super;
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MCRegister Reg = *Super;
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if (!MRI->reg_empty(Reg))
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LICalc->extendToUses(LR, Reg);
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}
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@ -371,7 +371,7 @@ static void createSegmentsForValues(LiveRange &LR,
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void LiveIntervals::extendSegmentsToUses(LiveRange &Segments,
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ShrinkToUsesWorkList &WorkList,
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unsigned Reg, LaneBitmask LaneMask) {
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Register Reg, LaneBitmask LaneMask) {
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// Keep track of the PHIs that are in use.
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SmallPtrSet<VNInfo*, 8> UsedPHIs;
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// Blocks that have already been added to WorkList as live-out.
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@ -470,7 +470,7 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
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ShrinkToUsesWorkList WorkList;
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// Visit all instructions reading li->reg().
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unsigned Reg = li->reg();
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Register Reg = li->reg();
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for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
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if (UseMI.isDebugValue() || !UseMI.readsVirtualRegister(Reg))
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continue;
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@ -523,7 +523,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI,
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// Is the register live before? Otherwise we may have to add a read-undef
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// flag for subregister defs.
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unsigned VReg = LI.reg();
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Register VReg = LI.reg();
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if (MRI->shouldTrackSubRegLiveness(VReg)) {
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if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
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MachineInstr *MI = getInstructionFromIndex(Def);
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@ -557,7 +557,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI,
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return MayHaveSplitComponents;
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}
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void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg) {
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void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, Register Reg) {
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LLVM_DEBUG(dbgs() << "Shrink: " << SR << '\n');
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assert(Register::isVirtualRegister(Reg) &&
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"Can only shrink virtual registers");
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@ -706,7 +706,7 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
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LiveRange::const_iterator>, 4> SRs;
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = Register::index2VirtReg(i);
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Register Reg = Register::index2VirtReg(i);
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if (MRI->reg_nodbg_empty(Reg))
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continue;
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const LiveInterval &LI = getInterval(Reg);
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@ -881,8 +881,8 @@ float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
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}
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LiveRange::Segment
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LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst) {
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LiveInterval& Interval = createEmptyInterval(reg);
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LiveIntervals::addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst) {
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LiveInterval &Interval = createEmptyInterval(Reg);
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VNInfo *VN = Interval.getNextValue(
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SlotIndex(getInstructionIndex(startInst).getRegSlot()),
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getVNInfoAllocator());
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@ -1049,7 +1049,7 @@ public:
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private:
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/// Update a single live range, assuming an instruction has been moved from
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/// OldIdx to NewIdx.
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void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) {
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void updateRange(LiveRange &LR, Register Reg, LaneBitmask LaneMask) {
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if (!Updated.insert(&LR).second)
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return;
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LLVM_DEBUG({
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@ -1246,7 +1246,7 @@ private:
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/// Update LR to reflect an instruction has been moved upwards from OldIdx
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/// to NewIdx (NewIdx < OldIdx).
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void handleMoveUp(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) {
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void handleMoveUp(LiveRange &LR, Register Reg, LaneBitmask LaneMask) {
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LiveRange::iterator E = LR.end();
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// Segment going into OldIdx.
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LiveRange::iterator OldIdxIn = LR.find(OldIdx.getBaseIndex());
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@ -1428,7 +1428,7 @@ private:
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}
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// Return the last use of reg between NewIdx and OldIdx.
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SlotIndex findLastUseBefore(SlotIndex Before, unsigned Reg,
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SlotIndex findLastUseBefore(SlotIndex Before, Register Reg,
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LaneBitmask LaneMask) {
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if (Register::isVirtualRegister(Reg)) {
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SlotIndex LastUse = Before;
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@ -1541,17 +1541,17 @@ void LiveIntervals::handleMoveIntoNewBundle(MachineInstr &BundleStart,
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void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
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const MachineBasicBlock::iterator End,
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const SlotIndex endIdx,
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LiveRange &LR, const unsigned Reg,
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const SlotIndex EndIdx, LiveRange &LR,
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const Register Reg,
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LaneBitmask LaneMask) {
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LiveInterval::iterator LII = LR.find(endIdx);
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LiveInterval::iterator LII = LR.find(EndIdx);
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SlotIndex lastUseIdx;
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if (LII == LR.begin()) {
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// This happens when the function is called for a subregister that only
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// occurs _after_ the range that is to be repaired.
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return;
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}
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if (LII != LR.end() && LII->start < endIdx)
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if (LII != LR.end() && LII->start < EndIdx)
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lastUseIdx = LII->end;
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else
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--LII;
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@ -1645,11 +1645,11 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
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while (End != MBB->end() && !Indexes->hasIndex(*End))
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++End;
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SlotIndex endIdx;
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SlotIndex EndIdx;
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if (End == MBB->end())
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endIdx = getMBBEndIdx(MBB).getPrevSlot();
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EndIdx = getMBBEndIdx(MBB).getPrevSlot();
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else
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endIdx = getInstructionIndex(*End);
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EndIdx = getInstructionIndex(*End);
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Indexes->repairIndexesInRange(MBB, Begin, End);
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@ -1678,9 +1678,9 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
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continue;
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for (LiveInterval::SubRange &S : LI.subranges())
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repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
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repairOldRegInRange(Begin, End, EndIdx, S, Reg, S.LaneMask);
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repairOldRegInRange(Begin, End, endIdx, LI, Reg);
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repairOldRegInRange(Begin, End, EndIdx, LI, Reg);
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}
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}
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@ -1717,7 +1717,7 @@ void LiveIntervals::splitSeparateComponents(LiveInterval &LI,
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if (NumComp <= 1)
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return;
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LLVM_DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');
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unsigned Reg = LI.reg();
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Register Reg = LI.reg();
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const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
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for (unsigned I = 1; I < NumComp; ++I) {
|
||||
Register NewVReg = MRI->createVirtualRegister(RegClass);
|
||||
|
||||
@ -82,11 +82,10 @@ LLVM_DUMP_METHOD void LiveVariables::VarInfo::dump() const {
|
||||
#endif
|
||||
|
||||
/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
|
||||
LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
|
||||
assert(Register::isVirtualRegister(RegIdx) &&
|
||||
"getVarInfo: not a virtual register!");
|
||||
VirtRegInfo.grow(RegIdx);
|
||||
return VirtRegInfo[RegIdx];
|
||||
LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) {
|
||||
assert(Reg.isVirtual() && "getVarInfo: not a virtual register!");
|
||||
VirtRegInfo.grow(Reg);
|
||||
return VirtRegInfo[Reg];
|
||||
}
|
||||
|
||||
void LiveVariables::MarkVirtRegAliveInBlock(
|
||||
@ -127,13 +126,13 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
|
||||
}
|
||||
}
|
||||
|
||||
void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
|
||||
void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB,
|
||||
MachineInstr &MI) {
|
||||
assert(MRI->getVRegDef(reg) && "Register use before def!");
|
||||
assert(MRI->getVRegDef(Reg) && "Register use before def!");
|
||||
|
||||
unsigned BBNum = MBB->getNumber();
|
||||
|
||||
VarInfo& VRInfo = getVarInfo(reg);
|
||||
VarInfo &VRInfo = getVarInfo(Reg);
|
||||
|
||||
// Check to see if this basic block is already a kill block.
|
||||
if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
|
||||
@ -164,7 +163,8 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
|
||||
// where there is a use in a PHI node that's a predecessor to the defining
|
||||
// block. We don't want to mark all predecessors as having the value "alive"
|
||||
// in this case.
|
||||
if (MBB == MRI->getVRegDef(reg)->getParent()) return;
|
||||
if (MBB == MRI->getVRegDef(Reg)->getParent())
|
||||
return;
|
||||
|
||||
// Add a new kill entry for this basic block. If this virtual register is
|
||||
// already marked as alive in this basic block, that means it is alive in at
|
||||
@ -175,10 +175,10 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
|
||||
// Update all dominating blocks to mark them as "known live".
|
||||
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
|
||||
E = MBB->pred_end(); PI != E; ++PI)
|
||||
MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
|
||||
MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), *PI);
|
||||
}
|
||||
|
||||
void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) {
|
||||
void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
|
||||
VarInfo &VRInfo = getVarInfo(Reg);
|
||||
|
||||
if (VRInfo.AliveBlocks.empty())
|
||||
@ -188,8 +188,9 @@ void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) {
|
||||
|
||||
/// FindLastPartialDef - Return the last partial def of the specified register.
|
||||
/// Also returns the sub-registers that're defined by the instruction.
|
||||
MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
|
||||
SmallSet<unsigned,4> &PartDefRegs) {
|
||||
MachineInstr *
|
||||
LiveVariables::FindLastPartialDef(Register Reg,
|
||||
SmallSet<unsigned, 4> &PartDefRegs) {
|
||||
unsigned LastDefReg = 0;
|
||||
unsigned LastDefDist = 0;
|
||||
MachineInstr *LastDef = nullptr;
|
||||
@ -227,7 +228,7 @@ MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
|
||||
/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
|
||||
/// implicit defs to a machine instruction if there was an earlier def of its
|
||||
/// super-register.
|
||||
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) {
|
||||
void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
|
||||
MachineInstr *LastDef = PhysRegDef[Reg];
|
||||
// If there was a previous use or a "full" def all is well.
|
||||
if (!LastDef && !PhysRegUse[Reg]) {
|
||||
@ -277,7 +278,7 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) {
|
||||
|
||||
/// FindLastRefOrPartRef - Return the last reference or partial reference of
|
||||
/// the specified register.
|
||||
MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
|
||||
MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {
|
||||
MachineInstr *LastDef = PhysRegDef[Reg];
|
||||
MachineInstr *LastUse = PhysRegUse[Reg];
|
||||
if (!LastDef && !LastUse)
|
||||
@ -307,7 +308,7 @@ MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
|
||||
return LastRefOrPartRef;
|
||||
}
|
||||
|
||||
bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
|
||||
bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
|
||||
MachineInstr *LastDef = PhysRegDef[Reg];
|
||||
MachineInstr *LastUse = PhysRegUse[Reg];
|
||||
if (!LastDef && !LastUse)
|
||||
@ -439,7 +440,7 @@ void LiveVariables::HandleRegMask(const MachineOperand &MO) {
|
||||
}
|
||||
}
|
||||
|
||||
void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
|
||||
void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI,
|
||||
SmallVectorImpl<unsigned> &Defs) {
|
||||
// What parts of the register are previously defined?
|
||||
SmallSet<unsigned, 32> Live;
|
||||
@ -485,7 +486,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
|
||||
void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
|
||||
SmallVectorImpl<unsigned> &Defs) {
|
||||
while (!Defs.empty()) {
|
||||
unsigned Reg = Defs.back();
|
||||
Register Reg = Defs.back();
|
||||
Defs.pop_back();
|
||||
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
|
||||
SubRegs.isValid(); ++SubRegs) {
|
||||
@ -652,7 +653,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
|
||||
// Convert and transfer the dead / killed information we have gathered into
|
||||
// VirtRegInfo onto MI's.
|
||||
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
|
||||
const unsigned Reg = Register::index2VirtReg(i);
|
||||
const Register Reg = Register::index2VirtReg(i);
|
||||
for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
|
||||
if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
|
||||
VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
|
||||
@ -677,7 +678,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
|
||||
|
||||
/// replaceKillInstruction - Update register kill info by replacing a kill
|
||||
/// instruction with a new one.
|
||||
void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
|
||||
void LiveVariables::replaceKillInstruction(Register Reg, MachineInstr &OldMI,
|
||||
MachineInstr &NewMI) {
|
||||
VarInfo &VI = getVarInfo(Reg);
|
||||
std::replace(VI.Kills.begin(), VI.Kills.end(), &OldMI, &NewMI);
|
||||
@ -717,8 +718,7 @@ void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
|
||||
}
|
||||
|
||||
bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
|
||||
unsigned Reg,
|
||||
MachineRegisterInfo &MRI) {
|
||||
Register Reg, MachineRegisterInfo &MRI) {
|
||||
unsigned Num = MBB.getNumber();
|
||||
|
||||
// Reg is live-through.
|
||||
@ -734,7 +734,7 @@ bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
|
||||
return findKill(&MBB);
|
||||
}
|
||||
|
||||
bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
|
||||
bool LiveVariables::isLiveOut(Register Reg, const MachineBasicBlock &MBB) {
|
||||
LiveVariables::VarInfo &VI = getVarInfo(Reg);
|
||||
|
||||
SmallPtrSet<const MachineBasicBlock *, 8> Kills;
|
||||
@ -792,7 +792,7 @@ void LiveVariables::addNewBlock(MachineBasicBlock *BB,
|
||||
|
||||
// Update info for all live variables
|
||||
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
|
||||
unsigned Reg = Register::index2VirtReg(i);
|
||||
Register Reg = Register::index2VirtReg(i);
|
||||
|
||||
// If the Defs is defined in the successor it can't be live in BB.
|
||||
if (Defs.count(Reg))
|
||||
@ -818,7 +818,7 @@ void LiveVariables::addNewBlock(MachineBasicBlock *BB,
|
||||
|
||||
SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()];
|
||||
for (auto R = BV.begin(), E = BV.end(); R != E; R++) {
|
||||
unsigned VirtReg = Register::index2VirtReg(*R);
|
||||
Register VirtReg = Register::index2VirtReg(*R);
|
||||
LiveVariables::VarInfo &VI = getVarInfo(VirtReg);
|
||||
VI.AliveBlocks.set(NumNew);
|
||||
}
|
||||
|
||||
@ -101,10 +101,10 @@ namespace {
|
||||
|
||||
// These functions are temporary abstractions around LiveVariables and
|
||||
// LiveIntervals, so they can go away when LiveVariables does.
|
||||
bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
|
||||
bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
|
||||
bool isLiveIn(Register Reg, const MachineBasicBlock *MBB);
|
||||
bool isLiveOutPastPHIs(Register Reg, const MachineBasicBlock *MBB);
|
||||
|
||||
using BBVRegPair = std::pair<unsigned, unsigned>;
|
||||
using BBVRegPair = std::pair<unsigned, Register>;
|
||||
using VRegPHIUse = DenseMap<BBVRegPair, unsigned>;
|
||||
|
||||
VRegPHIUse VRegPHIUseCount;
|
||||
@ -692,7 +692,7 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
|
||||
return Changed;
|
||||
}
|
||||
|
||||
bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
|
||||
bool PHIElimination::isLiveIn(Register Reg, const MachineBasicBlock *MBB) {
|
||||
assert((LV || LIS) &&
|
||||
"isLiveIn() requires either LiveVariables or LiveIntervals");
|
||||
if (LIS)
|
||||
@ -701,7 +701,7 @@ bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
|
||||
return LV->isLiveIn(Reg, *MBB);
|
||||
}
|
||||
|
||||
bool PHIElimination::isLiveOutPastPHIs(unsigned Reg,
|
||||
bool PHIElimination::isLiveOutPastPHIs(Register Reg,
|
||||
const MachineBasicBlock *MBB) {
|
||||
assert((LV || LIS) &&
|
||||
"isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user