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Revert r312724 ("[ARM] Remove redundant vcvt patterns.").
It leads to some improvements, but also a regression for the simple case, so it's not clearly a good idea. test/CodeGen/ARM/vcvt.ll now has test coverage to show the difference. Ultimately, the right solution is probably to custom-lower fp-to-int conversions, to something like ARMISD::VCVT_F32_S32 plus a bitcast. It's hard to do the right thing when the implicit bitcast isn't visible to DAG transforms. llvm-svn: 314169
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@ -1435,6 +1435,9 @@ def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
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let Predicates=[HasVFP2, HasDPVFP] in {
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def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
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(COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
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def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
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(VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
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}
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def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
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@ -1452,6 +1455,10 @@ def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
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def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
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(COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
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def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
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addrmode5:$ptr),
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(VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
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def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
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@ -1471,6 +1478,9 @@ def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
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let Predicates=[HasVFP2, HasDPVFP] in {
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def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
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(COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
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def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
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(VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
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}
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def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
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@ -1488,6 +1498,10 @@ def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
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def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
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(COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
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def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
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addrmode5:$ptr),
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(VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
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def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
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@ -355,9 +355,11 @@ define i32 @multi_sint(double %c, i32* nocapture %p, i32* nocapture %q) {
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov d16, r0, r1
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; CHECK-NEXT: vcvt.s32.f64 s0, d16
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: str r0, [r2]
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; CHECK-NEXT: str r0, [r3]
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; CHECK-NEXT: vstr s0, [r2]
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; CHECK-NEXT: vcvt.s32.f64 s0, d16
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; CHECK-NEXT: vcvt.s32.f64 s2, d16
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vstr s0, [r3]
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; CHECK-NEXT: mov pc, lr
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%conv = fptosi double %c to i32
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store i32 %conv, i32* %p, align 4
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@ -370,9 +372,11 @@ define i32 @multi_uint(double %c, i32* nocapture %p, i32* nocapture %q) {
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov d16, r0, r1
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; CHECK-NEXT: vcvt.u32.f64 s0, d16
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: str r0, [r2]
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; CHECK-NEXT: str r0, [r3]
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; CHECK-NEXT: vstr s0, [r2]
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; CHECK-NEXT: vcvt.u32.f64 s0, d16
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; CHECK-NEXT: vcvt.u32.f64 s2, d16
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vstr s0, [r3]
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; CHECK-NEXT: mov pc, lr
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%conv = fptoui double %c to i32
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store i32 %conv, i32* %p, align 4
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@ -385,8 +389,7 @@ define void @double_to_sint_store(double %c, i32* nocapture %p) {
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov d16, r0, r1
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; CHECK-NEXT: vcvt.s32.f64 s0, d16
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: str r0, [r2]
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; CHECK-NEXT: vstr s0, [r2]
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; CHECK-NEXT: mov pc, lr
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%conv = fptosi double %c to i32
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store i32 %conv, i32* %p, align 4
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@ -398,8 +401,7 @@ define void @double_to_uint_store(double %c, i32* nocapture %p) {
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov d16, r0, r1
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; CHECK-NEXT: vcvt.u32.f64 s0, d16
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: str r0, [r2]
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; CHECK-NEXT: vstr s0, [r2]
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; CHECK-NEXT: mov pc, lr
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%conv = fptoui double %c to i32
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store i32 %conv, i32* %p, align 4
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@ -411,8 +413,7 @@ define void @float_to_sint_store(float %c, i32* nocapture %p) {
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvt.s32.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: str r0, [r1]
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; CHECK-NEXT: vstr s0, [r1]
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; CHECK-NEXT: mov pc, lr
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%conv = fptosi float %c to i32
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store i32 %conv, i32* %p, align 4
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@ -424,8 +425,7 @@ define void @float_to_uint_store(float %c, i32* nocapture %p) {
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; CHECK: @ BB#0:
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvt.u32.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: str r0, [r1]
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; CHECK-NEXT: vstr s0, [r1]
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; CHECK-NEXT: mov pc, lr
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%conv = fptoui float %c to i32
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store i32 %conv, i32* %p, align 4
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