RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity

Thumb2 size reduction fix for tied operands of tMUL.

Browse Source 
The tied source operand of tMUL is the second source operand, not the
first like every other two-address thumb instruction. Special case it
in the size reduction pass to make sure we create the tMUL instruction
properly.

llvm-svn: 151315
This commit is contained in:
Jim Grosbach 2012-02-24 00:33:36 +00:00
parent 46bbb96031
commit 4ff2fb2fbc
4 changed files with 18 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -597,7 +597,19 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned Reg0 = MI->getOperand(0).getReg();
unsigned Reg1 = MI->getOperand(1).getReg();
if (Reg0 != Reg1) {
// t2MUL is "special". The tied source operand is second, not first.
if (MI->getOpcode() == ARM::t2MUL) {
if (Reg0 != MI->getOperand(2).getReg()) {
// If the other operand also isn't the same as the destination, we
// can't reduce.
if (Reg1 != Reg0)
return false;
// Try to commute the operands to make it a 2-address instruction.
MachineInstr *CommutedMI = TII->commuteInstruction(MI);
if (!CommutedMI)
return false;
}
} else if (Reg0 != Reg1) {
// Try to commute the operands to make it a 2-address instruction.
unsigned CommOpIdx1, CommOpIdx2;
if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||

6
test/CodeGen/ARM/avoid-cpsr-rmw.ll
View File

@ -6,9 +6,9 @@
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry:
; CHECK: t1:
; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r0, r1
; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
%0 = mul nsw i32 %a, %b
%1 = mul nsw i32 %c, %d
%2 = mul nsw i32 %0, %1

2
test/CodeGen/Thumb2/thumb2-mls.ll
View File

@ -15,5 +15,5 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
ret i32 %tmp2
}
; CHECK: f2:
; CHECK: muls r0, r0, r1
; CHECK: muls r0, r1, r0

2
test/CodeGen/Thumb2/thumb2-mul.ll
View File

@ -2,7 +2,7 @@
define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK: f1:
; CHECK: muls r0, r0, r1
; CHECK: muls r0, r1, r0
%tmp = mul i32 %a, %b
ret i32 %tmp
}