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AMDGPU: Refactor getBaseWithOffsetUsingSplitOR usage
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@ -191,6 +191,9 @@ private:
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bool isUniformLoad(const SDNode *N) const;
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bool isUniformBr(const SDNode *N) const;
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bool isBaseWithConstantOffset64(SDValue Addr, SDValue &LHS,
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SDValue &RHS) const;
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MachineSDNode *buildSMovImm64(SDLoc &DL, uint64_t Val, EVT VT) const;
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SDNode *glueCopyToOp(SDNode *N, SDValue NewChain, SDValue Glue) const;
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@ -928,6 +931,53 @@ bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
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Term->getMetadata("structurizecfg.uniform");
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}
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static bool getBaseWithOffsetUsingSplitOR(SelectionDAG &DAG, SDValue Addr,
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SDValue &N0, SDValue &N1) {
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if (Addr.getValueType() == MVT::i64 && Addr.getOpcode() == ISD::BITCAST &&
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Addr.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
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// As we split 64-bit `or` earlier, it's complicated pattern to match, i.e.
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// (i64 (bitcast (v2i32 (build_vector
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// (or (extract_vector_elt V, 0), OFFSET),
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// (extract_vector_elt V, 1)))))
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SDValue Lo = Addr.getOperand(0).getOperand(0);
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if (Lo.getOpcode() == ISD::OR && DAG.isBaseWithConstantOffset(Lo)) {
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SDValue BaseLo = Lo.getOperand(0);
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SDValue BaseHi = Addr.getOperand(0).getOperand(1);
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// Check that split base (Lo and Hi) are extracted from the same one.
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if (BaseLo.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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BaseHi.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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BaseLo.getOperand(0) == BaseHi.getOperand(0) &&
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// Lo is statically extracted from index 0.
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isa<ConstantSDNode>(BaseLo.getOperand(1)) &&
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BaseLo.getConstantOperandVal(1) == 0 &&
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// Hi is statically extracted from index 0.
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isa<ConstantSDNode>(BaseHi.getOperand(1)) &&
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BaseHi.getConstantOperandVal(1) == 1) {
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N0 = BaseLo.getOperand(0).getOperand(0);
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N1 = Lo.getOperand(1);
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return true;
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}
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}
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}
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return false;
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}
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bool AMDGPUDAGToDAGISel::isBaseWithConstantOffset64(SDValue Addr, SDValue &LHS,
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SDValue &RHS) const {
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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LHS = Addr.getOperand(0);
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RHS = Addr.getOperand(1);
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return true;
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}
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if (getBaseWithOffsetUsingSplitOR(*CurDAG, Addr, LHS, RHS)) {
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assert(LHS && RHS && isa<ConstantSDNode>(RHS));
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return true;
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}
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return false;
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}
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StringRef AMDGPUDAGToDAGISel::getPassName() const {
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return "AMDGPU DAG->DAG Pattern Instruction Selection";
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}
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@ -1660,37 +1710,6 @@ static MemSDNode* findMemSDNode(SDNode *N) {
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llvm_unreachable("cannot find MemSDNode in the pattern!");
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}
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static bool getBaseWithOffsetUsingSplitOR(SelectionDAG &DAG, SDValue Addr,
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SDValue &N0, SDValue &N1) {
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if (Addr.getValueType() == MVT::i64 && Addr.getOpcode() == ISD::BITCAST &&
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Addr.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
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// As we split 64-bit `or` earlier, it's complicated pattern to match, i.e.
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// (i64 (bitcast (v2i32 (build_vector
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// (or (extract_vector_elt V, 0), OFFSET),
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// (extract_vector_elt V, 1)))))
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SDValue Lo = Addr.getOperand(0).getOperand(0);
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if (Lo.getOpcode() == ISD::OR && DAG.isBaseWithConstantOffset(Lo)) {
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SDValue BaseLo = Lo.getOperand(0);
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SDValue BaseHi = Addr.getOperand(0).getOperand(1);
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// Check that split base (Lo and Hi) are extracted from the same one.
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if (BaseLo.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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BaseHi.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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BaseLo.getOperand(0) == BaseHi.getOperand(0) &&
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// Lo is statically extracted from index 0.
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isa<ConstantSDNode>(BaseLo.getOperand(1)) &&
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BaseLo.getConstantOperandVal(1) == 0 &&
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// Hi is statically extracted from index 0.
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isa<ConstantSDNode>(BaseHi.getOperand(1)) &&
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BaseHi.getConstantOperandVal(1) == 1) {
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N0 = BaseLo.getOperand(0).getOperand(0);
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N1 = Lo.getOperand(1);
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return true;
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}
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}
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}
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return false;
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}
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template <bool IsSigned>
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bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDNode *N,
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SDValue Addr,
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@ -1704,13 +1723,7 @@ bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDNode *N,
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(!Subtarget->hasFlatSegmentOffsetBug() ||
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AS != AMDGPUAS::FLAT_ADDRESS)) {
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SDValue N0, N1;
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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N0 = Addr.getOperand(0);
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N1 = Addr.getOperand(1);
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} else if (getBaseWithOffsetUsingSplitOR(*CurDAG, Addr, N0, N1)) {
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assert(N0 && N1 && isa<ConstantSDNode>(N1));
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}
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if (N0 && N1) {
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if (isBaseWithConstantOffset64(Addr, N0, N1)) {
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uint64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
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const SIInstrInfo *TII = Subtarget->getInstrInfo();
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