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ARM: disallow pc as a base register in Thumb2 memory ops.

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These should all be deferring to the "OP (literal)" variant according to the
ARM ARM.

llvm-svn: 261895
This commit is contained in:
Tim Northover 2016-02-25 16:54:52 +00:00
parent 3d17e7bc47
commit 50249c2bb2
3 changed files with 18 additions and 2 deletions
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2
lib/Target/ARM/ARMInstrThumb2.td
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@ -270,7 +270,7 @@ def t2addrmode_so_reg : MemOperand,
let EncoderMethod = "getT2AddrModeSORegOpValue"; let EncoderMethod = "getT2AddrModeSORegOpValue";
let DecoderMethod = "DecodeT2AddrModeSOReg"; let DecoderMethod = "DecodeT2AddrModeSOReg";
let ParserMatchClass = t2addrmode_so_reg_asmoperand; let ParserMatchClass = t2addrmode_so_reg_asmoperand;
let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm); let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
} }
// Addresses for the TBB/TBH instructions. // Addresses for the TBB/TBH instructions.

2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -1226,7 +1226,7 @@ public:
} }
bool isT2MemRegOffset() const { bool isT2MemRegOffset() const {
if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
Memory.Alignment != 0) Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
return false; return false;
// Only lsl #{0, 1, 2, 3} allowed. // Only lsl #{0, 1, 2, 3} allowed.
if (Memory.ShiftType == ARM_AM::no_shift) if (Memory.ShiftType == ARM_AM::no_shift)

16
test/MC/ARM/thumb2-diagnostics.s
View File

@ -102,3 +102,19 @@ foo2:
@ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction
@ PC is not valid as base of load
ldr r0, [pc, r0]
ldrb r1, [pc, r2]
ldrh r3, [pc, r3]
pld r4, [pc, r5]
str r6, [pc, r7]
strb r7 [pc, r8]
strh r9, [pc, r10]
@ CHECK-ERRORS: error: instruction requires: arm-mode
@ CHECK-ERRORS: error: instruction requires: arm-mode
@ CHECK-ERRORS: error: instruction requires: arm-mode
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: instruction requires: arm-mode
@ CHECK-ERRORS: error: immediate value expected for vector index
@ CHECK-ERRORS: error: instruction requires: arm-mode