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AMDGPU/SI: use S_MOV_B64 for larger copies in copyPhysReg
Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15629 llvm-svn: 256073
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@ -326,15 +326,31 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
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};
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static const int16_t Sub0_15_64[] = {
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AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
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AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
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AMDGPU::sub8_sub9, AMDGPU::sub10_sub11,
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AMDGPU::sub12_sub13, AMDGPU::sub14_sub15,
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};
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static const int16_t Sub0_7[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
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};
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static const int16_t Sub0_7_64[] = {
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AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
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AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
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};
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static const int16_t Sub0_3[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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};
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static const int16_t Sub0_3_64[] = {
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AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
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};
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static const int16_t Sub0_2[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2,
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};
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@ -376,18 +392,18 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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} else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_3;
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Opcode = AMDGPU::S_MOV_B64;
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SubIndices = Sub0_3_64;
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} else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_7;
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Opcode = AMDGPU::S_MOV_B64;
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SubIndices = Sub0_7_64;
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} else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_15;
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Opcode = AMDGPU::S_MOV_B64;
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SubIndices = Sub0_15_64;
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} else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
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assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
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