1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00

set up some infrastructure, some minor cleanups.

llvm-svn: 95260
This commit is contained in:
Chris Lattner 2010-02-03 21:43:43 +00:00
parent 5c8b1b9164
commit 5078a382e4

View File

@ -13,23 +13,31 @@
#define DEBUG_TYPE "x86-emitter"
#include "X86.h"
#include "X86TargetMachine.h"
#include "X86InstrInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
class X86MCCodeEmitter : public MCCodeEmitter {
X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
X86TargetMachine &TM;
const TargetMachine &TM;
const TargetInstrInfo &TII;
public:
X86MCCodeEmitter(X86TargetMachine &tm) : TM(tm) {
X86MCCodeEmitter(TargetMachine &tm)
: TM(tm), TII(*TM.getInstrInfo()) {
}
~X86MCCodeEmitter() {}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
void EmitByte(unsigned char C, raw_ostream &OS) const {
OS << (char)C;
}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const;
};
} // end anonymous namespace
@ -37,5 +45,31 @@ public:
MCCodeEmitter *llvm::createX86MCCodeEmitter(const Target &,
TargetMachine &TM) {
return new X86MCCodeEmitter(static_cast<X86TargetMachine&>(TM));
return new X86MCCodeEmitter(TM);
}
void X86MCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
unsigned Opcode = MI.getOpcode();
const TargetInstrDesc &Desc = TII.get(Opcode);
// Emit the lock opcode prefix as needed.
if (Desc.TSFlags & X86II::LOCK)
EmitByte(0xF0, OS);
// Emit segment override opcode prefix as needed.
switch (Desc.TSFlags & X86II::SegOvrMask) {
default: assert(0 && "Invalid segment!");
case 0: break; // No segment override!
case X86II::FS:
EmitByte(0x64, OS);
break;
case X86II::GS:
EmitByte(0x65, OS);
break;
}
}