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Reapply "[mips][FastISel] Implement shift ops for Mips fast-isel.""
This reapplies r235194, which was reverted in r235495 because it was causing a failure in our out-of-tree buildbots for MIPS. With the sign-extension patch in r235718, this patch doesn't cause any problem any more. llvm-svn: 235878
This commit is contained in:
Vasileios Kalintiris
parent
90ad4f9b98
commit
50a170aec4
@ -100,6 +100,7 @@ private:
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bool selectRet(const Instruction *I);
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bool selectTrunc(const Instruction *I);
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bool selectIntExt(const Instruction *I);
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bool selectShift(const Instruction *I);
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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@ -1413,6 +1414,81 @@ unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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return Success ? DestReg : 0;
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}
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bool MipsFastISel::selectShift(const Instruction *I) {
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MVT RetVT;
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if (!isTypeSupported(I->getType(), RetVT))
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return false;
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unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
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if (!ResultReg)
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return false;
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unsigned Opcode = I->getOpcode();
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const Value *Op0 = I->getOperand(0);
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unsigned Op0Reg = getRegForValue(Op0);
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if (!Op0Reg)
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return false;
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// If AShr or LShr, then we need to make sure the operand0 is sign extended.
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if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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if (!TempReg)
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return false;
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MVT Op0MVT = TLI.getValueType(Op0->getType(), true).getSimpleVT();
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bool IsZExt = Opcode == Instruction::LShr;
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if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
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return false;
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Op0Reg = TempReg;
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}
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if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
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uint64_t ShiftVal = C->getZExtValue();
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switch (Opcode) {
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default:
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llvm_unreachable("Unexpected instruction.");
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case Instruction::Shl:
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Opcode = Mips::SLL;
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break;
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case Instruction::AShr:
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Opcode = Mips::SRA;
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break;
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case Instruction::LShr:
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Opcode = Mips::SRL;
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break;
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}
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emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
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updateValueMap(I, ResultReg);
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return true;
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}
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unsigned Op1Reg = getRegForValue(I->getOperand(1));
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if (!Op1Reg)
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return false;
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switch (Opcode) {
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default:
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llvm_unreachable("Unexpected instruction.");
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case Instruction::Shl:
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Opcode = Mips::SLLV;
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break;
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case Instruction::AShr:
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Opcode = Mips::SRAV;
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break;
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case Instruction::LShr:
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Opcode = Mips::SRLV;
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break;
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}
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emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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updateValueMap(I, ResultReg);
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return true;
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}
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bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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if (!TargetSupported)
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return false;
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@ -1423,6 +1499,10 @@ bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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return selectLoad(I);
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case Instruction::Store:
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return selectStore(I);
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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return selectShift(I);
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case Instruction::And:
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case Instruction::Or:
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case Instruction::Xor:
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122
test/CodeGen/Mips/Fast-ISel/shftopm.ll
Normal file
122
test/CodeGen/Mips/Fast-ISel/shftopm.ll
Normal file
@ -0,0 +1,122 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \
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; RUN: -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \
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; RUN: -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
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@s1 = global i16 -89, align 2
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@s2 = global i16 4, align 2
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@us1 = global i16 -503, align 2
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@us2 = global i16 5, align 2
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@s3 = common global i16 0, align 2
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@us3 = common global i16 0, align 2
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define void @sll() {
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entry:
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%0 = load i16, i16* @s1, align 2
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%1 = load i16, i16* @s2, align 2
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%shl = shl i16 %0, %1
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store i16 %shl, i16* @s3, align 2
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; CHECK-LABEL: sll:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
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; CHECK-DAG: lw $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]])
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; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
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; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
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; CHECK: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]]
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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define void @slli() {
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entry:
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%0 = load i16, i16* @s1, align 2
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%shl = shl i16 %0, 5
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store i16 %shl, i16* @s3, align 2
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; CHECK-LABEL: slli:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
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; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
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; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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define void @srl() {
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entry:
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%0 = load i16, i16* @us1, align 2
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%1 = load i16, i16* @us2, align 2
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%shr = lshr i16 %0, %1
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store i16 %shr, i16* @us3, align 2
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ret void
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; CHECK-LABEL: srl:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
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; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
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; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
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; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
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; CHECK: srlv $[[RES:[0-9]+]], $[[US1]], $[[US2]]
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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}
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define void @srli() {
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entry:
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%0 = load i16, i16* @us1, align 2
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%shr = lshr i16 %0, 4
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store i16 %shr, i16* @us3, align 2
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; CHECK-LABEL: srli:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
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; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
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; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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define void @sra() {
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entry:
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%0 = load i16, i16* @s1, align 2
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%1 = load i16, i16* @s2, align 2
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%shr = ashr i16 %0, %1
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store i16 %shr, i16* @s3, align 2
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; CHECK-LABEL: sra:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
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; CHECK-DAG: lw $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]])
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; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
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; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
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; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]]
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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define void @srai() {
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entry:
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%0 = load i16, i16* @s1, align 2
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%shr = ashr i16 %0, 2
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store i16 %shr, i16* @s3, align 2
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; CHECK-LABEL: srai:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
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; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
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; CHECK: sra $[[RES:[0-9]+]], $[[S1]], 2
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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