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AMDGPU: Move zeroed FP high bits optimization to patterns
This commit is contained in:
Matt Arsenault
parent
cbac628d6a
commit
50b757aa13
@ -44,6 +44,63 @@ class R600InstrInfo;
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namespace {
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// Instructions that will be lowered with a final instruction that zeros the
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// high result bits.
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// XXX - only need to list legal operations.
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static bool fp16SrcZerosHighBits(unsigned Opc) {
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switch (Opc) {
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::FMA:
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case ISD::FMAD:
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case ISD::FCANONICALIZE:
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case ISD::FP_ROUND:
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case ISD::UINT_TO_FP:
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case ISD::SINT_TO_FP:
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case ISD::FABS:
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// Fabs is lowered to a bit operation, but it's an and which will clear the
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// high bits anyway.
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FPOWI:
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case ISD::FPOW:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FCEIL:
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case ISD::FTRUNC:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FROUND:
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case ISD::FFLOOR:
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case ISD::FMINNUM:
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case ISD::FMAXNUM:
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case AMDGPUISD::FRACT:
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case AMDGPUISD::CLAMP:
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case AMDGPUISD::COS_HW:
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case AMDGPUISD::SIN_HW:
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case AMDGPUISD::FMIN3:
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case AMDGPUISD::FMAX3:
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case AMDGPUISD::FMED3:
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case AMDGPUISD::FMAD_FTZ:
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case AMDGPUISD::RCP:
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case AMDGPUISD::RSQ:
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case AMDGPUISD::RCP_IFLAG:
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case AMDGPUISD::LDEXP:
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return true;
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default:
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// fcopysign, select and others may be lowered to 32-bit bit operations
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// which don't zero the high bits.
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return false;
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}
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}
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static bool isNullConstantOrUndef(SDValue V) {
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if (V.isUndef())
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return true;
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@ -4353,7 +4353,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(CVT_PK_I16_I32)
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NODE_NAME_CASE(CVT_PK_U16_U32)
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NODE_NAME_CASE(FP_TO_FP16)
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NODE_NAME_CASE(FP16_ZEXT)
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NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
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NODE_NAME_CASE(CONST_DATA_PTR)
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NODE_NAME_CASE(PC_ADD_REL_OFFSET)
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@ -4483,8 +4482,7 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
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break;
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}
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case AMDGPUISD::FP_TO_FP16:
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case AMDGPUISD::FP16_ZEXT: {
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case AMDGPUISD::FP_TO_FP16: {
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unsigned BitWidth = Known.getBitWidth();
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// High bits are zero.
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@ -4631,7 +4629,6 @@ unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
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case AMDGPUISD::BUFFER_LOAD_USHORT:
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return 16;
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case AMDGPUISD::FP_TO_FP16:
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case AMDGPUISD::FP16_ZEXT:
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return 16;
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default:
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return 1;
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@ -457,9 +457,6 @@ enum NodeType : unsigned {
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// are known 0.
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FP_TO_FP16,
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// Wrapper around fp16 results that are known to zero the high bits.
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FP16_ZEXT,
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/// This node is for VLIW targets and it is used to represent a vector
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/// that is stored in consecutive registers with the same channel.
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/// For example:
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@ -132,7 +132,6 @@ def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFP
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def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
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def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
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def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
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def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
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def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
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@ -9375,63 +9375,6 @@ SDValue SITargetLowering::performXorCombine(SDNode *N,
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return SDValue();
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}
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// Instructions that will be lowered with a final instruction that zeros the
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// high result bits.
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// XXX - probably only need to list legal operations.
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static bool fp16SrcZerosHighBits(unsigned Opc) {
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switch (Opc) {
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::FMA:
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case ISD::FMAD:
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case ISD::FCANONICALIZE:
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case ISD::FP_ROUND:
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case ISD::UINT_TO_FP:
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case ISD::SINT_TO_FP:
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case ISD::FABS:
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// Fabs is lowered to a bit operation, but it's an and which will clear the
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// high bits anyway.
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FPOWI:
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case ISD::FPOW:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FCEIL:
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case ISD::FTRUNC:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FROUND:
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case ISD::FFLOOR:
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case ISD::FMINNUM:
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case ISD::FMAXNUM:
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case AMDGPUISD::FRACT:
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case AMDGPUISD::CLAMP:
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case AMDGPUISD::COS_HW:
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case AMDGPUISD::SIN_HW:
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case AMDGPUISD::FMIN3:
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case AMDGPUISD::FMAX3:
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case AMDGPUISD::FMED3:
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case AMDGPUISD::FMAD_FTZ:
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case AMDGPUISD::RCP:
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case AMDGPUISD::RSQ:
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case AMDGPUISD::RCP_IFLAG:
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case AMDGPUISD::LDEXP:
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return true;
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default:
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// fcopysign, select and others may be lowered to 32-bit bit operations
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// which don't zero the high bits.
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return false;
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}
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}
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SDValue SITargetLowering::performZeroExtendCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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if (!Subtarget->has16BitInsts() ||
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@ -9446,15 +9389,6 @@ SDValue SITargetLowering::performZeroExtendCombine(SDNode *N,
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if (Src.getValueType() != MVT::i16)
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return SDValue();
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// (i32 zext (i16 (bitcast f16:$src))) -> fp16_zext $src
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// FIXME: It is not universally true that the high bits are zeroed on gfx9.
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if (Src.getOpcode() == ISD::BITCAST) {
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SDValue BCSrc = Src.getOperand(0);
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if (BCSrc.getValueType() == MVT::f16 &&
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fp16SrcZerosHighBits(BCSrc.getOpcode()))
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return DCI.DAG.getNode(AMDGPUISD::FP16_ZEXT, SDLoc(N), VT, BCSrc);
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}
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return SDValue();
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}
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@ -814,6 +814,12 @@ def NegSubInlineConstV216 : PatLeaf<(build_vector), [{
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(isNullConstantOrUndef(Src1) && isNegInlineImmediate(Src0.getNode()));
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}], getNegV2I16Imm>;
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def fp16_zeros_high_16bits : PatLeaf<(f16 VGPR_32:$src), [{
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return fp16SrcZerosHighBits(N->getOpcode());
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}]>;
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//===----------------------------------------------------------------------===//
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// MUBUF/SMEM Patterns
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//===----------------------------------------------------------------------===//
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@ -1992,11 +1992,13 @@ def : GCNPat <
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//===----------------------------------------------------------------------===//
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// Miscellaneous Patterns
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//===----------------------------------------------------------------------===//
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def : GCNPat <
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(i32 (AMDGPUfp16_zext f16:$src)),
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(COPY $src)
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>;
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// Eliminate a zero extension from an fp16 operation if it already
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// zeros the high bits of the 32-bit register.
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def : GCNPat<
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(i32 (zext (i16 (bitconvert fp16_zeros_high_16bits:$src)))),
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(COPY VSrc_b16:$src)
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>;
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def : GCNPat <
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(i32 (trunc i64:$a)),
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