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[AMDGPU] Make use of divideCeil. NFC.

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This commit is contained in:
Jay Foad 2020-03-26 13:39:51 +00:00
parent a62c51da79
commit 50b935813e
3 changed files with 4 additions and 7 deletions
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3
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
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@ -159,8 +159,7 @@ unsigned CFStack::getSubEntrySize(CFStack::StackItem Item) {
}
void CFStack::updateMaxStackSize() {
unsigned CurrentStackSize =
CurrentEntries + (alignTo(CurrentSubEntries, 4) / 4);
unsigned CurrentStackSize = CurrentEntries + divideCeil(CurrentSubEntries, 4);
MaxStackSize = std::max(CurrentStackSize, MaxStackSize);
}

2
lib/Target/AMDGPU/SIRegisterInfo.h
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@ -274,7 +274,7 @@ public:
// \returns a DWORD offset of a \p SubReg
unsigned getChannelFromSubReg(unsigned SubReg) const {
return SubReg ? alignTo(getSubRegIdxOffset(SubReg), 32) / 32 : 0;
return SubReg ? divideCeil(getSubRegIdxOffset(SubReg), 32) : 0;
}
// \returns a DWORD size of a \p SubReg

6
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
View File

@ -301,8 +301,7 @@ unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,
unsigned FlatWorkGroupSize) {
return alignTo(getMaxWavesPerCU(STI, FlatWorkGroupSize),
getEUsPerCU(STI)) / getEUsPerCU(STI);
return divideCeil(getMaxWavesPerCU(STI, FlatWorkGroupSize), getEUsPerCU(STI));
}
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) {
@ -316,8 +315,7 @@ unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) {
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
unsigned FlatWorkGroupSize) {
return alignTo(FlatWorkGroupSize, getWavefrontSize(STI)) /
getWavefrontSize(STI);
return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
}
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {