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[CostModel][X86] Added mul costs for vXi8 vectors

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More realistic v16i8/v32i8/v64i8 MUL costs - we have to extend to vXi16, use PMULLW and then truncate the result

llvm-svn: 286838
This commit is contained in:
Simon Pilgrim 2016-11-14 15:54:24 +00:00
parent bf629ee6cc
commit 50c2f1dd68
2 changed files with 39 additions and 21 deletions
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26
lib/Target/X86/X86TargetTransformInfo.cpp
View File

@ -218,15 +218,19 @@ int X86TTIImpl::getArithmeticInstrCost(
}
static const CostTblEntry AVX512BWCostTable[] = {
{ ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence.
{ ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence.
{ ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence.
// Vectorizing division is a bad idea. See the SSE2 table for more comments.
{ ISD::SDIV, MVT::v64i8, 64*20 },
{ ISD::SDIV, MVT::v32i16, 32*20 },
{ ISD::SDIV, MVT::v16i32, 16*20 },
{ ISD::SDIV, MVT::v8i64, 8*20 },
{ ISD::SDIV, MVT::v8i64, 8*20 },
{ ISD::UDIV, MVT::v64i8, 64*20 },
{ ISD::UDIV, MVT::v32i16, 32*20 },
{ ISD::UDIV, MVT::v16i32, 16*20 },
{ ISD::UDIV, MVT::v8i64, 8*20 },
{ ISD::UDIV, MVT::v8i64, 8*20 },
};
// Look for AVX512BW lowering tricks for custom cases.
@ -240,9 +244,12 @@ int X86TTIImpl::getArithmeticInstrCost(
{ ISD::SHL, MVT::v16i32, 1 },
{ ISD::SRL, MVT::v16i32, 1 },
{ ISD::SRA, MVT::v16i32, 1 },
{ ISD::SHL, MVT::v8i64, 1 },
{ ISD::SRL, MVT::v8i64, 1 },
{ ISD::SRA, MVT::v8i64, 1 },
{ ISD::SHL, MVT::v8i64, 1 },
{ ISD::SRL, MVT::v8i64, 1 },
{ ISD::SRA, MVT::v8i64, 1 },
{ ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence.
{ ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence.
};
if (ST->hasAVX512()) {
@ -324,6 +331,10 @@ int X86TTIImpl::getArithmeticInstrCost(
{ ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence.
{ ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence.
{ ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
{ ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence.
{ ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence.
{ ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/
{ ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
{ ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
@ -340,12 +351,15 @@ int X86TTIImpl::getArithmeticInstrCost(
}
static const CostTblEntry AVXCustomCostTable[] = {
{ ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence.
{ ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/
{ ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
{ ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
{ ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/
{ ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/
{ ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/
// Vectorizing division is a bad idea. See the SSE2 table for more comments.
{ ISD::SDIV, MVT::v32i8, 32*20 },
{ ISD::SDIV, MVT::v16i16, 16*20 },
@ -494,6 +508,8 @@ int X86TTIImpl::getArithmeticInstrCost(
{ ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence.
{ ISD::SRA, MVT::v4i64, 2*12 }, // srl/xor/sub sequence.
{ ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence.
{ ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/
{ ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/
{ ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/

34
test/Analysis/CostModel/X86/arith.ll
View File

@ -490,24 +490,26 @@ define i32 @mul(i32 %arg) {
; AVX512BW: cost of 1 {{.*}} %I = mul
%I = mul <32 x i16> undef, undef
; SSSE3: cost of 2 {{.*}} %J = mul
; SSE42: cost of 2 {{.*}} %J = mul
; AVX: cost of 2 {{.*}} %J = mul
; AVX2: cost of 2 {{.*}} %J = mul
; AVX512: cost of 2 {{.*}} %J = mul
; SSSE3: cost of 12 {{.*}} %J = mul
; SSE42: cost of 12 {{.*}} %J = mul
; AVX: cost of 12 {{.*}} %J = mul
; AVX2: cost of 7 {{.*}} %J = mul
; AVX512F: cost of 5 {{.*}} %J = mul
; AVX512BW: cost of 4 {{.*}} %J = mul
%J = mul <16 x i8> undef, undef
; SSSE3: cost of 4 {{.*}} %K = mul
; SSE42: cost of 4 {{.*}} %K = mul
; AVX: cost of 2 {{.*}} %K = mul
; AVX2: cost of 2 {{.*}} %K = mul
; AVX512: cost of 2 {{.*}} %K = mul
; SSSE3: cost of 24 {{.*}} %K = mul
; SSE42: cost of 24 {{.*}} %K = mul
; AVX: cost of 26 {{.*}} %K = mul
; AVX2: cost of 17 {{.*}} %K = mul
; AVX512F: cost of 13 {{.*}} %K = mul
; AVX512BW: cost of 4 {{.*}} %K = mul
%K = mul <32 x i8> undef, undef
; SSSE3: cost of 8 {{.*}} %L = mul
; SSE42: cost of 8 {{.*}} %L = mul
; AVX: cost of 4 {{.*}} %L = mul
; AVX2: cost of 4 {{.*}} %L = mul
; AVX512F: cost of 4 {{.*}} %L = mul
; AVX512BW: cost of 2 {{.*}} %L = mul
; SSSE3: cost of 48 {{.*}} %L = mul
; SSE42: cost of 48 {{.*}} %L = mul
; AVX: cost of 52 {{.*}} %L = mul
; AVX2: cost of 34 {{.*}} %L = mul
; AVX512F: cost of 26 {{.*}} %L = mul
; AVX512BW: cost of 11 {{.*}} %L = mul
%L = mul <64 x i8> undef, undef
ret i32 undef