RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity

[RISCV] Enable the use of the old mucounteren name

Browse Source 
The RISC-V Privileged Specification 1.11 defines `mcountinhibit`, which
has the same numeric CSR value as `mucounteren` from 1.09.1. This patch
enables the use of the old `mucounteren` name.

Patch by Yuichi Sugiyama.

Reviewed By: lenary, jrtc27, pzheng

Differential Revision: https://reviews.llvm.org/D85067
This commit is contained in:
Sam Elliott 2020-08-17 13:10:27 +01:00
parent 74d7198e6b
commit 510c5643ce
2 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/RISCV/RISCVSystemOperands.td
View File

@ -310,7 +310,9 @@ def: SysReg<"mhpmcounter31h", 0xB9F>;
//===--------------------------
// Machine Counter Setup
//===--------------------------
let AltName = "mucounteren" in // Privileged spec v1.9.1 Name
def : SysReg<"mcountinhibit", 0x320>;
def : SysReg<"mhpmevent3", 0x323>;
def : SysReg<"mhpmevent4", 0x324>;
def : SysReg<"mhpmevent5", 0x325>;

14
test/MC/RISCV/machine-csr-names.s
View File

@ -863,6 +863,20 @@ csrrs t1, mcountinhibit, zero
# uimm12
csrrs t2, 0x320, zero
# mucounteren
# name
# CHECK-INST: csrrs t1, mcountinhibit, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x32]
# CHECK-INST-ALIAS: csrr t1, mcountinhibit
# uimm12
# CHECK-INST: csrrs t2, mcountinhibit, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x32]
# CHECK-INST-ALIAS: csrr t2, mcountinhibit
# name
csrrs t1, mucounteren, zero
# uimm12
csrrs t2, 0x320, zero
# mhpmevent3
# name
# CHECK-INST: csrrs t1, mhpmevent3, zero