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[Hexagon] Generate PIC-specific versions of save/restore routines
In PIC mode, the registers R14, R15 and R28 are reserved for use by the PLT handling code. This causes all functions to clobber these registers. While this is not new for regular function calls, it does also apply to save/restore functions, which do not follow the standard ABI conventions with respect to the volatile/non-volatile registers. Patch by Jyotsna Verma. llvm-svn: 264324
This commit is contained in:
Krzysztof Parzyszek
parent
8edc6624b9
commit
513db043c7
@ -536,7 +536,8 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
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// Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
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// frame instruction if we encounter it.
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if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
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if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
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RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC) {
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MachineBasicBlock::iterator It = RetI;
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++It;
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// Delete all instructions after the RESTORE (except labels).
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@ -556,7 +557,8 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
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if (!MBB.empty() && InsertPt != MBB.begin()) {
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MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
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unsigned COpc = PrevIt->getOpcode();
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if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
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if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
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COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC)
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NeedsDeallocframe = false;
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}
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@ -922,10 +924,16 @@ bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
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if (useSpillFunction(MF, CSI)) {
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unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
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const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem);
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auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
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bool IsPIC = HTM.getRelocationModel() == Reloc::PIC_;
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// Call spill function.
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DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
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unsigned SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
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: Hexagon::SAVE_REGISTERS_CALL_V4;
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MachineInstr *SaveRegsCall =
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BuildMI(MBB, MI, DL, HII.get(Hexagon::SAVE_REGISTERS_CALL_V4))
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BuildMI(MBB, MI, DL, HII.get(SpillOpc))
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.addExternalSymbol(SpillFun);
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// Add callee-saved registers as use.
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addCalleeSaveRegistersAsImpOperand(SaveRegsCall, MaxReg, false);
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@ -965,6 +973,8 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
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unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
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SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem;
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const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
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auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
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bool IsPIC = HTM.getRelocationModel() == Reloc::PIC_;
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// Call spill function.
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DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
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@ -972,14 +982,16 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
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MachineInstr *DeallocCall = nullptr;
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if (HasTC) {
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unsigned ROpc = Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
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unsigned ROpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
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: Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
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DeallocCall = BuildMI(MBB, MI, DL, HII.get(ROpc))
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.addExternalSymbol(RestoreFn);
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} else {
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// The block has a return.
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MachineBasicBlock::iterator It = MBB.getFirstTerminator();
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assert(It->isReturn() && std::next(It) == MBB.end());
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unsigned ROpc = Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
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unsigned ROpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
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: Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
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DeallocCall = BuildMI(MBB, It, DL, HII.get(ROpc))
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.addExternalSymbol(RestoreFn);
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// Transfer the function live-out registers.
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@ -2354,7 +2354,9 @@ bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
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bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
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return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
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MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
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MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
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MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
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MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
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}
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@ -3282,21 +3282,41 @@ let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
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Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
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def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
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let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">;
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}
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}
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// Restore registers and dealloc frame before a tail call.
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let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel;
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel;
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let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<"">, PredRel;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<"">, PredRel;
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}
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}
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// Save registers function call.
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let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
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def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
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let isExtended = 1, opExtendable = 0 in
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def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel;
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def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel;
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let Defs = [R14, R15, R28] in
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def SAVE_REGISTERS_CALL_V4_PIC : T_Call<"">, PredRel;
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let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
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def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<"">, PredRel;
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}
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//===----------------------------------------------------------------------===//
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69
test/CodeGen/Hexagon/pic-regusage.ll
Normal file
69
test/CodeGen/Hexagon/pic-regusage.ll
Normal file
@ -0,0 +1,69 @@
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; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
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; Force the use of R14 (by clobbering everything else in the inline asm).
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; Make sure that R14 is not set before the __save call (which will clobber
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; R14, R15 and R28).
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; CHECK: call __save_r16_through_r27
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; CHECK: }
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; CHECK: r14{{ *}}=
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@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
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; Function Attrs: nounwind optsize
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define i32 @_Z7testR14Pi(i32* nocapture %res) #0 {
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entry:
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%0 = load i32, i32* %res, align 4
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%1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27}"(i32 %0, i32 40, i32 50) #1
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%asmresult = extractvalue { i32, i32 } %1, 0
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%asmresult1 = extractvalue { i32, i32 } %1, 1
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store i32 %asmresult, i32* %res, align 4
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%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2
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%2 = load i32, i32* %res, align 4
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%call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2
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ret i32 0
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}
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; Function Attrs: nounwind optsize
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declare i32 @printf(i8*, ...) #0
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; Same as above for R15.
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; CHECK: call __save_r16_through_r27
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; CHECK: }
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; CHECK: r15{{ *}}=
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; Function Attrs: nounwind optsize
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define i32 @_Z7testR15Pi(i32* nocapture %res) #0 {
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entry:
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%0 = load i32, i32* %res, align 4
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%1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27}"(i32 %0, i32 40, i32 50) #1
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%asmresult = extractvalue { i32, i32 } %1, 0
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%asmresult1 = extractvalue { i32, i32 } %1, 1
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store i32 %asmresult, i32* %res, align 4
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%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2
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%2 = load i32, i32* %res, align 4
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%call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2
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ret i32 0
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}
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; Same as above for R28.
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; CHECK: call __save_r16_through_r27
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; CHECK: }
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; CHECK: r28{{ *}}=
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; Function Attrs: nounwind optsize
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define i32 @_Z7testR28Pi(i32* nocapture %res) #0 {
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entry:
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%0 = load i32, i32* %res, align 4
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%1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26}"(i32 %0, i32 40, i32 50) #1
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%asmresult = extractvalue { i32, i32 } %1, 0
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%asmresult1 = extractvalue { i32, i32 } %1, 1
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store i32 %asmresult, i32* %res, align 4
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%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2
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%2 = load i32, i32* %res, align 4
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%call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2
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ret i32 0
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}
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attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind optsize }
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