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https://github.com/RPCS3/llvm-mirror.git
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MISched: Don't schedule regions with 0 instructions
I think this is correct, but may not necessarily be the correct fix for the assertion I'm really trying to solve. If a scheduling region was found that only has dbg_value instructions, the RegPressure tracker would end up in an inconsistent state because it would skip over any debug instructions and point to an instruction outside of the scheduling region. It may still be possible for this to happen if there are some real schedulable instructions between dbg_values, but I haven't managed to break this. The testcase is extremely sensitive and I'm not sure how to make it more resistent to future scheduler changes that would avoid stressing this situation. llvm-svn: 356926
This commit is contained in:
Matt Arsenault
parent
43880afb99
commit
5163fa047f
@ -486,13 +486,17 @@ getSchedRegions(MachineBasicBlock *MBB,
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MachineInstr &MI = *std::prev(I);
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if (isSchedBoundary(&MI, &*MBB, MF, TII))
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break;
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if (!MI.isDebugInstr())
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if (!MI.isDebugInstr()) {
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// MBB::size() uses instr_iterator to count. Here we need a bundle to
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// count as a single instruction.
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++NumRegionInstrs;
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}
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}
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Regions.push_back(SchedRegion(I, RegionEnd, NumRegionInstrs));
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// It's possible we found a scheduling region that only has debug
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// instructions. Don't bother scheduling these.
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if (NumRegionInstrs != 0)
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Regions.push_back(SchedRegion(I, RegionEnd, NumRegionInstrs));
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}
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if (RegionsTopDown)
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115
test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
Normal file
115
test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
Normal file
@ -0,0 +1,115 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
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# The sequence of DBG_VALUEs forms a scheduling region with 0 real
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# instructions. The RegPressure tracker would end up skipping over any
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# debug instructions, so it would point to the instruction
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# before/outside of the region, hitting this assert:
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# assert((BotRPTracker.getPos() == RegionEnd ||
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# (RegionEnd->isDebugInstr() &&
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# BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
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# "Can't find the region bottom");
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---
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name: only_dbg_value_sched_region
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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waveLimiter: true
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body: |
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; CHECK-LABEL: name: only_dbg_value_sched_region
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, 0, implicit $exec
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; CHECK: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, 0, implicit $exec
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; CHECK: undef %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec
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; CHECK: %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
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; CHECK: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: undef %11.sub1:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]
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; CHECK: undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $exec
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; CHECK: dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $exec
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; CHECK: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, implicit $exec
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; CHECK: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $exec
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; CHECK: %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $exec
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; CHECK: GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, implicit $exec
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; CHECK: %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, 0, implicit $exec
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; CHECK: [[DEF2]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, 0, implicit $exec
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; CHECK: dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, implicit $exec
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; CHECK: dead %21:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF4]], 0, 0, 0, implicit $exec
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; CHECK: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 2, [[DEF2]], implicit $exec
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; CHECK: dead %22:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF5]], 0, 0, 0, implicit $exec
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; CHECK: S_NOP 0, implicit [[DEF7]], implicit [[V_LSHLREV_B64_]].sub0, implicit [[DEF6]], implicit [[V_MOV_B32_e32_]]
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; CHECK: GLOBAL_STORE_DWORD [[DEF5]], [[V_MOV_B32_e32_1]], 0, 0, 0, implicit $exec
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: S_SETREG_IMM32_B32 0, 1
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; CHECK: DBG_VALUE
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; CHECK: DBG_VALUE
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; CHECK: DBG_VALUE
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; CHECK: S_SETREG_IMM32_B32 0, 1
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; CHECK: bb.2:
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; CHECK: S_NOP 0, implicit [[COPY]]
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; CHECK: S_NOP 0, implicit [[DEF8]]
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; CHECK: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0
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%0:vgpr_32 = COPY $vgpr0
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%1:vreg_64 = IMPLICIT_DEF
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%2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, 0, implicit $exec
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%3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, 0, implicit $exec
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undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec
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%4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
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%5:vreg_64 = COPY %2
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undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $exec
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%6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $exec
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%7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, 0, implicit $exec
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%8:vreg_64 = IMPLICIT_DEF
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%9:vreg_64 = IMPLICIT_DEF
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%10:vreg_64 = IMPLICIT_DEF
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undef %11.sub1:vreg_64 = IMPLICIT_DEF
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%12:vgpr_32 = IMPLICIT_DEF
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%13:vgpr_32 = IMPLICIT_DEF
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%14:vreg_64 = IMPLICIT_DEF
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%15:vreg_64 = IMPLICIT_DEF
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%16:vgpr_32 = IMPLICIT_DEF
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%17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $exec
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%19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $exec
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GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, implicit $exec
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%11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, 0, implicit $exec
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%8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, 0, implicit $exec
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%20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, implicit $exec
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%21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, 0, implicit $exec
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%22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, 0, implicit $exec
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%23:vreg_64 = V_LSHLREV_B64 2, %8, implicit $exec
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S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17
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GLOBAL_STORE_DWORD %15, %18, 0, 0, 0, implicit $exec
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bb.1:
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S_SETREG_IMM32_B32 0, 1
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DBG_VALUE
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DBG_VALUE
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DBG_VALUE
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S_SETREG_IMM32_B32 0, 1
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bb.2:
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S_NOP 0, implicit %0
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S_NOP 0, implicit %16
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S_ENDPGM 0
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...
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