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https://github.com/RPCS3/llvm-mirror.git
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[SimplifyCFG] Rewrite SinkThenElseCodeToEnd
The new version has several advantages:
1) IMSHO it's more readable and neater
2) It handles loads and stores properly
3) It can handle any number of incoming blocks rather than just two. I'll be taking advantage of this in a followup patch.
With this change we can now finally sink load-modify-store idioms such as:
if (a)
return *b += 3;
else
return *b += 4;
=>
%z = load i32, i32* %y
%.sink = select i1 %a, i32 5, i32 7
%b = add i32 %z, %.sink
store i32 %b, i32* %y
ret i32 %b
When this works for switches it'll be even more powerful.
llvm-svn: 279229
This commit is contained in:
James Molloy
parent
205c3bad03
commit
5190268c1f
@ -1319,172 +1319,232 @@ HoistTerminator:
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return true;
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}
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// Return true if V0 and V1 are equivalent. This handles the obvious cases
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// where V0 == V1 and V0 and V1 are both identical instructions, but also
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// handles loads and stores with identical operands.
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//
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// Because determining if two memory instructions are equivalent
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// depends on control flow, the \c At0 and \c At1 parameters specify a
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// location for the query. This function is essentially answering the
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// query "If V0 were moved to At0, and V1 were moved to At1, are V0 and V1
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// equivalent?". In practice this means checking that moving V0 to At0
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// doesn't cross any other memory instructions.
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static bool areValuesTriviallySame(Value *V0, BasicBlock::const_iterator At0,
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Value *V1, BasicBlock::const_iterator At1) {
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if (V0 == V1)
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return true;
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// Also check for instructions that are identical but not pointer-identical.
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// This can include load instructions that haven't been CSE'd.
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if (!isa<Instruction>(V0) || !isa<Instruction>(V1))
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return false;
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const auto *I0 = cast<Instruction>(V0);
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const auto *I1 = cast<Instruction>(V1);
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if (!I0->isIdenticalToWhenDefined(I1))
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return false;
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if (!I0->mayReadOrWriteMemory())
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return true;
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// Instructions that may read or write memory have extra restrictions. We
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// must ensure we don't treat %a and %b as equivalent in code such as:
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//
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// %a = load %x
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// store %x, 1
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// if (%c) {
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// %b = load %x
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// %d = add %b, 1
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// } else {
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// %d = add %a, 1
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// }
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// Be conservative. We don't want to search the entire CFG between def
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// and use; if the def isn't in the same block as the use just bail.
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if (I0->getParent() != At0->getParent() ||
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I1->getParent() != At1->getParent())
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return false;
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// Again, be super conservative. Ideally we'd be able to query AliasAnalysis
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// but we currently don't have that available.
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auto WritesMemory = [](const Instruction &I) {
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return I.mayReadOrWriteMemory();
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};
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if (std::any_of(std::next(I0->getIterator()), At0, WritesMemory))
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return false;
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if (std::any_of(std::next(I1->getIterator()), At1, WritesMemory))
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return false;
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return true;
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}
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// Is it legal to replace the operand \c OpIdx of \c GEP with a PHI node?
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static bool canReplaceGEPOperandWithPHI(const Instruction *GEP,
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unsigned OpIdx) {
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if (OpIdx == 0)
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return true;
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gep_type_iterator It = std::next(gep_type_begin(GEP), OpIdx - 1);
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return !It->isStructTy();
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}
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// All blocks in Blocks unconditionally jump to a common successor. Analyze
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// the last non-terminator instruction in each block and return true if it would
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// be possible to sink them into their successor, creating one common
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// instruction instead. Set NumPHIsRequired to the number of PHI nodes that
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// would need to be created during sinking.
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static bool canSinkLastInstruction(ArrayRef<BasicBlock*> Blocks,
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unsigned &NumPHIsRequired) {
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SmallVector<Instruction*,4> Insts;
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for (auto *BB : Blocks) {
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if (BB->getTerminator() == &BB->front())
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// Block was empty.
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return false;
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Insts.push_back(BB->getTerminator()->getPrevNode());
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}
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// Prune out obviously bad instructions to move. Any non-store instruction
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// must have exactly one use, and we check later that use is by a single,
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// common PHI instruction in the successor.
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for (auto *I : Insts) {
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// These instructions may change or break semantics if moved.
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if (isa<PHINode>(I) || I->isEHPad() || isa<AllocaInst>(I) ||
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I->getType()->isTokenTy())
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return false;
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// Apart from loads and stores, we won't move anything that could
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// change memory or have sideeffects.
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if (!isa<StoreInst>(I) && !isa<LoadInst>(I) &&
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(I->mayHaveSideEffects() || I->mayHaveSideEffects()))
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return false;
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// Everything must have only one use too, apart from stores which
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// have no uses.
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if (!isa<StoreInst>(I) && !I->hasOneUse())
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return false;
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}
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const Instruction *I0 = Insts.front();
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for (auto *I : Insts)
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if (!I->isSameOperationAs(I0))
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return false;
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// If this isn't a store, check the only user is a single PHI.
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if (!isa<StoreInst>(I0)) {
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auto *PNUse = dyn_cast<PHINode>(*I0->user_begin());
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if (!PNUse ||
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!all_of(Insts, [&PNUse](const Instruction *I) {
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return *I->user_begin() == PNUse;
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}))
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return false;
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}
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NumPHIsRequired = 0;
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for (unsigned OI = 0, OE = I0->getNumOperands(); OI != OE; ++OI) {
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if (I0->getOperand(OI)->getType()->isTokenTy())
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// Don't touch any operand of token type.
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return false;
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auto SameAsI0 = [&I0, OI](const Instruction *I) {
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return areValuesTriviallySame(I->getOperand(OI), I->getIterator(),
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I0->getOperand(OI), I0->getIterator());
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};
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if (!all_of(Insts, SameAsI0)) {
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if (isa<GetElementPtrInst>(I0) && !canReplaceGEPOperandWithPHI(I0, OI))
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// We can't create a PHI from this GEP.
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return false;
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if (isa<ShuffleVectorInst>(I0) && OI == 2)
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// We can't create a PHI for a shufflevector mask.
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return false;
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++NumPHIsRequired;
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}
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}
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return true;
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}
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// Assuming canSinkLastInstruction(Blocks) has returned true, sink the last
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// instruction of every block in Blocks to their common successor, commoning
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// into one instruction.
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static void sinkLastInstruction(ArrayRef<BasicBlock*> Blocks) {
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unsigned Dummy;
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(void)Dummy;
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assert(canSinkLastInstruction(Blocks, Dummy) &&
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"Must analyze before transforming!");
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auto *BBEnd = Blocks[0]->getTerminator()->getSuccessor(0);
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// canSinkLastInstruction returning true guarantees that every block has at
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// least one non-terminator instruction.
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SmallVector<Instruction*,4> Insts;
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for (auto *BB : Blocks)
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Insts.push_back(BB->getTerminator()->getPrevNode());
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// We don't need to do any checking here; canSinkLastInstruction should have
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// done it all for us.
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Instruction *I0 = Insts.front();
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SmallVector<Value*, 4> NewOperands;
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for (unsigned O = 0, E = I0->getNumOperands(); O != E; ++O) {
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// This check is different to that in canSinkLastInstruction. There, we
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// cared about the global view once simplifycfg (and instcombine) have
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// completed - it takes into account PHIs that become trivially
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// simplifiable. However here we need a more local view; if an operand
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// differs we create a PHI and rely on instcombine to clean up the very
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// small mess we may make.
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bool NeedPHI = any_of(Insts, [&I0, O](const Instruction *I) {
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return I->getOperand(O) != I0->getOperand(O);
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});
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if (!NeedPHI) {
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NewOperands.push_back(I0->getOperand(O));
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continue;
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}
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// Create a new PHI in the successor block and populate it.
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auto *Op = I0->getOperand(O);
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assert(!Op->getType()->isTokenTy() && "Can't PHI tokens!");
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auto *PN = PHINode::Create(Op->getType(), Insts.size(),
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Op->getName() + ".sink", &BBEnd->front());
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for (auto *I : Insts)
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PN->addIncoming(I->getOperand(O), I->getParent());
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NewOperands.push_back(PN);
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}
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// Arbitrarily use I0 as the new "common" instruction; remap its operands
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// and move it to the start of the successor block.
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for (unsigned O = 0, E = I0->getNumOperands(); O != E; ++O)
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I0->getOperandUse(O).set(NewOperands[O]);
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I0->moveBefore(&*BBEnd->getFirstInsertionPt());
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if (!isa<StoreInst>(I0)) {
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// canSinkLastInstruction checked that all instructions were used by
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// one and only one PHI node. Find that now, RAUW it to our common
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// instruction and nuke it.
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assert(I0->hasOneUse());
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auto *PN = cast<PHINode>(*I0->user_begin());
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PN->replaceAllUsesWith(I0);
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PN->eraseFromParent();
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}
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// Finally nuke all instructions apart from the common instruction.
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for (auto *I : Insts)
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if (I != I0)
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I->eraseFromParent();
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}
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/// Given an unconditional branch that goes to BBEnd,
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/// check whether BBEnd has only two predecessors and the other predecessor
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/// ends with an unconditional branch. If it is true, sink any common code
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/// in the two predecessors to BBEnd.
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static bool SinkThenElseCodeToEnd(BranchInst *BI1) {
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assert(BI1->isUnconditional());
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BasicBlock *BB1 = BI1->getParent();
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BasicBlock *BBEnd = BI1->getSuccessor(0);
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// Check that BBEnd has two predecessors and the other predecessor ends with
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// an unconditional branch.
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pred_iterator PI = pred_begin(BBEnd), PE = pred_end(BBEnd);
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BasicBlock *Pred0 = *PI++;
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if (PI == PE) // Only one predecessor.
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SmallVector<BasicBlock*,4> Blocks;
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for (auto *BB : predecessors(BBEnd))
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Blocks.push_back(BB);
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if (Blocks.size() != 2 ||
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!all_of(Blocks, [](const BasicBlock *BB) {
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auto *BI = dyn_cast<BranchInst>(BB->getTerminator());
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return BI && BI->isUnconditional();
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}))
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return false;
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BasicBlock *Pred1 = *PI++;
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if (PI != PE) // More than two predecessors.
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return false;
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BasicBlock *BB2 = (Pred0 == BB1) ? Pred1 : Pred0;
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BranchInst *BI2 = dyn_cast<BranchInst>(BB2->getTerminator());
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if (!BI2 || !BI2->isUnconditional())
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return false;
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// Gather the PHI nodes in BBEnd.
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SmallDenseMap<std::pair<Value *, Value *>, PHINode *> JointValueMap;
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Instruction *FirstNonPhiInBBEnd = nullptr;
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for (BasicBlock::iterator I = BBEnd->begin(), E = BBEnd->end(); I != E; ++I) {
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if (PHINode *PN = dyn_cast<PHINode>(I)) {
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Value *BB1V = PN->getIncomingValueForBlock(BB1);
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Value *BB2V = PN->getIncomingValueForBlock(BB2);
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JointValueMap[std::make_pair(BB1V, BB2V)] = PN;
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} else {
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FirstNonPhiInBBEnd = &*I;
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break;
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}
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}
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if (!FirstNonPhiInBBEnd)
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return false;
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// This does very trivial matching, with limited scanning, to find identical
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// instructions in the two blocks. We scan backward for obviously identical
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// instructions in an identical order.
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BasicBlock::InstListType::reverse_iterator RI1 = BB1->getInstList().rbegin(),
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RE1 = BB1->getInstList().rend(),
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RI2 = BB2->getInstList().rbegin(),
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RE2 = BB2->getInstList().rend();
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// Skip debug info.
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while (RI1 != RE1 && isa<DbgInfoIntrinsic>(&*RI1))
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++RI1;
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if (RI1 == RE1)
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return false;
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while (RI2 != RE2 && isa<DbgInfoIntrinsic>(&*RI2))
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++RI2;
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if (RI2 == RE2)
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return false;
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// Skip the unconditional branches.
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++RI1;
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++RI2;
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bool Changed = false;
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while (RI1 != RE1 && RI2 != RE2) {
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// Skip debug info.
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while (RI1 != RE1 && isa<DbgInfoIntrinsic>(&*RI1))
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++RI1;
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if (RI1 == RE1)
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return Changed;
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while (RI2 != RE2 && isa<DbgInfoIntrinsic>(&*RI2))
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++RI2;
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if (RI2 == RE2)
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return Changed;
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Instruction *I1 = &*RI1, *I2 = &*RI2;
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auto InstPair = std::make_pair(I1, I2);
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// I1 and I2 should have a single use in the same PHI node, and they
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// perform the same operation.
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// Cannot move control-flow-involving, volatile loads, vaarg, etc.
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if (isa<PHINode>(I1) || isa<PHINode>(I2) || isa<TerminatorInst>(I1) ||
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isa<TerminatorInst>(I2) || I1->isEHPad() || I2->isEHPad() ||
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isa<AllocaInst>(I1) || isa<AllocaInst>(I2) ||
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I1->mayHaveSideEffects() || I2->mayHaveSideEffects() ||
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I1->mayReadOrWriteMemory() || I2->mayReadOrWriteMemory() ||
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!I1->hasOneUse() || !I2->hasOneUse() || !JointValueMap.count(InstPair))
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return Changed;
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// Check whether we should swap the operands of ICmpInst.
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// TODO: Add support of communativity.
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ICmpInst *ICmp1 = dyn_cast<ICmpInst>(I1), *ICmp2 = dyn_cast<ICmpInst>(I2);
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bool SwapOpnds = false;
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if (ICmp1 && ICmp2 && ICmp1->getOperand(0) != ICmp2->getOperand(0) &&
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ICmp1->getOperand(1) != ICmp2->getOperand(1) &&
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(ICmp1->getOperand(0) == ICmp2->getOperand(1) ||
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ICmp1->getOperand(1) == ICmp2->getOperand(0))) {
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ICmp2->swapOperands();
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SwapOpnds = true;
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}
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if (!I1->isSameOperationAs(I2)) {
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if (SwapOpnds)
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ICmp2->swapOperands();
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return Changed;
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}
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// The operands should be either the same or they need to be generated
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// with a PHI node after sinking. We only handle the case where there is
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// a single pair of different operands.
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Value *DifferentOp1 = nullptr, *DifferentOp2 = nullptr;
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unsigned Op1Idx = ~0U;
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for (unsigned I = 0, E = I1->getNumOperands(); I != E; ++I) {
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if (I1->getOperand(I) == I2->getOperand(I))
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continue;
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// Early exit if we have more-than one pair of different operands or if
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// we need a PHI node to replace a constant.
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if (Op1Idx != ~0U || isa<Constant>(I1->getOperand(I)) ||
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isa<Constant>(I2->getOperand(I))) {
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// If we can't sink the instructions, undo the swapping.
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if (SwapOpnds)
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ICmp2->swapOperands();
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return Changed;
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}
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DifferentOp1 = I1->getOperand(I);
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Op1Idx = I;
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DifferentOp2 = I2->getOperand(I);
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}
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DEBUG(dbgs() << "SINK common instructions " << *I1 << "\n");
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DEBUG(dbgs() << " " << *I2 << "\n");
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// We insert the pair of different operands to JointValueMap and
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// remove (I1, I2) from JointValueMap.
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if (Op1Idx != ~0U) {
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auto &NewPN = JointValueMap[std::make_pair(DifferentOp1, DifferentOp2)];
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if (!NewPN) {
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NewPN =
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PHINode::Create(DifferentOp1->getType(), 2,
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DifferentOp1->getName() + ".sink", &BBEnd->front());
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NewPN->addIncoming(DifferentOp1, BB1);
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NewPN->addIncoming(DifferentOp2, BB2);
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DEBUG(dbgs() << "Create PHI node " << *NewPN << "\n";);
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}
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// I1 should use NewPN instead of DifferentOp1.
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I1->setOperand(Op1Idx, NewPN);
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}
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PHINode *OldPN = JointValueMap[InstPair];
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JointValueMap.erase(InstPair);
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// We need to update RE1 and RE2 if we are going to sink the first
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// instruction in the basic block down.
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bool UpdateRE1 = (I1 == &BB1->front()), UpdateRE2 = (I2 == &BB2->front());
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// Sink the instruction.
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BBEnd->getInstList().splice(FirstNonPhiInBBEnd->getIterator(),
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BB1->getInstList(), I1);
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if (!OldPN->use_empty())
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OldPN->replaceAllUsesWith(I1);
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OldPN->eraseFromParent();
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if (!I2->use_empty())
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I2->replaceAllUsesWith(I1);
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I1->intersectOptionalDataWith(I2);
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// TODO: Use combineMetadata here to preserve what metadata we can
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// (analogous to the hoisting case above).
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I2->eraseFromParent();
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if (UpdateRE1)
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RE1 = BB1->getInstList().rend();
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if (UpdateRE2)
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RE2 = BB2->getInstList().rend();
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FirstNonPhiInBBEnd = &*I1;
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unsigned NumPHIsToInsert;
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while (canSinkLastInstruction(Blocks, NumPHIsToInsert) && NumPHIsToInsert <= 1) {
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sinkLastInstruction(Blocks);
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NumSinkCommons++;
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Changed = true;
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}
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@ -106,7 +106,7 @@ if.then:
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if.else:
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store i32 3, i32* %p, align 4
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%incdec.ptr5 = getelementptr inbounds i32, i32* %p, i32 2
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%incdec.ptr5 = getelementptr inbounds i32, i32* %p, i32 3
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store i32 5, i32* %incdec.ptr1, align 4
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store i32 6, i32* %incdec.ptr5, align 4
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br label %if.end
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@ -9,8 +9,9 @@
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; return -1;
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; }
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; CHECK: mvnlt
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; CHECK: .loc 1 6 7
|
||||
; CHECK: mvn
|
||||
; CHECK: strlt
|
||||
|
||||
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
|
||||
target triple = "armv7--linux-gnueabihf"
|
||||
|
||||
@ -29,7 +29,8 @@ if.else: ; preds = %entry
|
||||
%4 = load double, double* %a, align 8
|
||||
%mul1 = fmul fast double %1, %4
|
||||
%sub1 = fsub fast double %mul1, %0
|
||||
store double %sub1, double* %y, align 8
|
||||
%gep1 = getelementptr double, double* %y, i32 1
|
||||
store double %sub1, double* %gep1, align 8
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
|
||||
@ -81,3 +81,204 @@ if.end:
|
||||
; CHECK: call
|
||||
; CHECK: add
|
||||
; CHECK-NOT: br
|
||||
|
||||
define i32 @test4(i1 zeroext %flag, i32 %x, i32* %y) {
|
||||
entry:
|
||||
br i1 %flag, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
%a = add i32 %x, 5
|
||||
store i32 %a, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.else:
|
||||
%b = add i32 %x, 7
|
||||
store i32 %b, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test4
|
||||
; CHECK: select
|
||||
; CHECK: store
|
||||
; CHECK-NOT: store
|
||||
|
||||
define i32 @test5(i1 zeroext %flag, i32 %x, i32* %y) {
|
||||
entry:
|
||||
br i1 %flag, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
%a = add i32 %x, 5
|
||||
store volatile i32 %a, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.else:
|
||||
%b = add i32 %x, 7
|
||||
store i32 %b, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test5
|
||||
; CHECK: store volatile
|
||||
; CHECK: store
|
||||
|
||||
define i32 @test6(i1 zeroext %flag, i32 %x, i32* %y) {
|
||||
entry:
|
||||
br i1 %flag, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
%a = add i32 %x, 5
|
||||
store volatile i32 %a, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.else:
|
||||
%b = add i32 %x, 7
|
||||
store volatile i32 %b, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test6
|
||||
; CHECK: select
|
||||
; CHECK: store volatile
|
||||
; CHECK-NOT: store
|
||||
|
||||
define i32 @test7(i1 zeroext %flag, i32 %x, i32* %y) {
|
||||
entry:
|
||||
br i1 %flag, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
%z = load volatile i32, i32* %y
|
||||
%a = add i32 %z, 5
|
||||
store volatile i32 %a, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.else:
|
||||
%w = load volatile i32, i32* %y
|
||||
%b = add i32 %w, 7
|
||||
store volatile i32 %b, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test7
|
||||
; CHECK-DAG: select
|
||||
; CHECK-DAG: load volatile
|
||||
; CHECK: store volatile
|
||||
; CHECK-NOT: load
|
||||
; CHECK-NOT: store
|
||||
|
||||
; %z and %w are in different blocks. We shouldn't sink the add because
|
||||
; there may be intervening memory instructions.
|
||||
define i32 @test8(i1 zeroext %flag, i32 %x, i32* %y) {
|
||||
entry:
|
||||
%z = load volatile i32, i32* %y
|
||||
br i1 %flag, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
%a = add i32 %z, 5
|
||||
store volatile i32 %a, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.else:
|
||||
%w = load volatile i32, i32* %y
|
||||
%b = add i32 %w, 7
|
||||
store volatile i32 %b, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test8
|
||||
; CHECK: add
|
||||
; CHECK: add
|
||||
|
||||
; The extra store in %if.then means %z and %w are not equivalent.
|
||||
define i32 @test9(i1 zeroext %flag, i32 %x, i32* %y, i32* %p) {
|
||||
entry:
|
||||
br i1 %flag, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
store i32 7, i32* %p
|
||||
%z = load volatile i32, i32* %y
|
||||
store i32 6, i32* %p
|
||||
%a = add i32 %z, 5
|
||||
store volatile i32 %a, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.else:
|
||||
%w = load volatile i32, i32* %y
|
||||
%b = add i32 %w, 7
|
||||
store volatile i32 %b, i32* %y
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test9
|
||||
; CHECK: add
|
||||
; CHECK: add
|
||||
|
||||
%struct.anon = type { i32, i32 }
|
||||
|
||||
; The GEP indexes a struct type so cannot have a variable last index.
|
||||
define i32 @test10(i1 zeroext %flag, i32 %x, i32* %y, %struct.anon* %s) {
|
||||
entry:
|
||||
br i1 %flag, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
%dummy = add i32 %x, 5
|
||||
%gepa = getelementptr inbounds %struct.anon, %struct.anon* %s, i32 0, i32 0
|
||||
store volatile i32 %x, i32* %gepa
|
||||
br label %if.end
|
||||
|
||||
if.else:
|
||||
%dummy1 = add i32 %x, 6
|
||||
%gepb = getelementptr inbounds %struct.anon, %struct.anon* %s, i32 0, i32 1
|
||||
store volatile i32 %x, i32* %gepb
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test10
|
||||
; CHECK: getelementptr
|
||||
; CHECK: getelementptr
|
||||
; CHECK: phi
|
||||
; CHECK: store volatile
|
||||
|
||||
; The shufflevector's mask operand cannot be merged in a PHI.
|
||||
define i32 @test11(i1 zeroext %flag, i32 %w, <2 x i32> %x, <2 x i32> %y) {
|
||||
entry:
|
||||
br i1 %flag, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
%dummy = add i32 %w, 5
|
||||
%sv1 = shufflevector <2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 0, i32 1>
|
||||
br label %if.end
|
||||
|
||||
if.else:
|
||||
%dummy1 = add i32 %w, 6
|
||||
%sv2 = shufflevector <2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 1, i32 0>
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
%p = phi <2 x i32> [ %sv1, %if.then ], [ %sv2, %if.else ]
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test11
|
||||
; CHECK: shufflevector
|
||||
; CHECK: shufflevector
|
||||
|
||||
Loading…
Reference in New Issue
Block a user