From 51affe9d3192045fb47e1ac1ec866028296b6113 Mon Sep 17 00:00:00 2001 From: Juergen Ributzka Date: Fri, 1 Aug 2014 18:04:14 +0000 Subject: [PATCH] [FastISel][ARM] Do not emit stores for undef arguments. This is a followup patch for r214366, which added the same behavior to the AArch64 and X86 FastISel code. This fix reproduces the already existing behavior of SelectionDAG in FastISel. llvm-svn: 214531 --- lib/Target/ARM/ARMFastISel.cpp | 6 ++++++ test/CodeGen/ARM/fast-isel-call.ll | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index e2d90cd9306..3433efc0d5e 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -1941,6 +1941,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl &Args, // Process the args. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; + const Value *ArgVal = Args[VA.getValNo()]; unsigned Arg = ArgRegs[VA.getValNo()]; MVT ArgVT = ArgVTs[VA.getValNo()]; @@ -2001,6 +2002,11 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl &Args, } else { assert(VA.isMemLoc()); // Need to store on the stack. + + // Don't emit stores for undef values. + if (isa(ArgVal)) + continue; + Address Addr; Addr.BaseType = Address::RegBase; Addr.Base.Reg = ARM::SP; diff --git a/test/CodeGen/ARM/fast-isel-call.ll b/test/CodeGen/ARM/fast-isel-call.ll index 2d7378e47f2..9d9e341647a 100644 --- a/test/CodeGen/ARM/fast-isel-call.ll +++ b/test/CodeGen/ARM/fast-isel-call.ll @@ -250,4 +250,19 @@ entry: ret void } +declare void @bar2(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) + +define void @call_undef_args() { +; ARM-LABEL: call_undef_args +; ARM: movw r0, #1 +; ARM-NEXT: movw r1, #2 +; ARM-NEXT: movw r2, #3 +; ARM-NEXT: movw r3, #4 +; ARM-NOT: str {{r[0-9]+}}, [sp] +; ARM: movw [[REG:l?r[0-9]*]], #6 +; ARM-NEXT: str [[REG]], [sp, #4] + call void @bar2(i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6) + ret void +} + declare void @print(float)