From 51b479815cf2ce170a1b275ecb9331c81cafa921 Mon Sep 17 00:00:00 2001 From: Ricky Taylor Date: Thu, 11 Mar 2021 20:35:04 +0000 Subject: [PATCH] [M68k] Introduce DReg bead This is required in order to determine during disassembly whether a Reg bead without associated DA bead is referring to a data register. Differential Revision: https://reviews.llvm.org/D98534 --- lib/Target/M68k/M68kInstrArithmetic.td | 34 +++++++++---------- lib/Target/M68k/M68kInstrBits.td | 6 ++-- lib/Target/M68k/M68kInstrFormats.td | 17 +++++----- lib/Target/M68k/M68kInstrShiftRotate.td | 6 ++-- lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h | 11 +++--- .../M68k/MCTargetDesc/M68kMCCodeEmitter.cpp | 2 ++ 6 files changed, 40 insertions(+), 36 deletions(-) diff --git a/lib/Target/M68k/M68kInstrArithmetic.td b/lib/Target/M68k/M68kInstrArithmetic.td index f4714d2534b..d6ecec07439 100644 --- a/lib/Target/M68k/M68kInstrArithmetic.td +++ b/lib/Target/M68k/M68kInstrArithmetic.td @@ -38,7 +38,7 @@ /// | | | EFFECTIVE ADDRESS /// x x x x | REG | OP MODE | MODE | REG /// ---------------------------------------------------- -class MxArithEncoding : MxEncoding; @@ -53,7 +53,7 @@ class MxArithEncoding + MxBeadDReg SRC, MxBeadDReg DST> : MxEncoding, SIZE, MxBead1Bit<0b1>, DST, CMD>; /// Encoding for Immediate forms @@ -88,13 +88,13 @@ let Defs = [CCR] in { let Constraints = "$src = $dst" in { // $reg, $ccr <- $reg op $reg -class MxBiArOp_RFRR_xEA CMD> +class MxBiArOp_RFRR_xEA CMD, MxBead REG> : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd), MN#"."#TYPE.Prefix#"\t$opd, $dst", [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))], MxArithEncoding, !cast("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"), - MxBeadReg<0>, + REG, !cast("MxEncEA"#TYPE.RLet#"_2"), MxExtEmpty>>; @@ -110,7 +110,7 @@ class MxBiArOp_RFRR_EAd CMD> [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))], MxArithEncoding, !cast("MxOpMode"#TYPE.Size#"EAd"), - MxBeadReg<2>, MxEncEAd_0, MxExtEmpty>>; + MxBeadDReg<2>, MxEncEAd_0, MxExtEmpty>>; // $reg <- $reg op $imm class MxBiArOp_RFRI_xEA CMD> @@ -119,7 +119,7 @@ class MxBiArOp_RFRI_xEA CMD> [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))], MxArithEncoding, !cast("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"), - MxBeadReg<0>, MxEncEAi, + MxBeadDReg<0>, MxEncEAi, !cast("MxExtI"#TYPE.Size#"_2")>>; // Again, there are two ways to write an immediate to Dn register either dEA @@ -141,7 +141,7 @@ class MxBiArOp_RFRM, !cast("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"), - MxBeadReg<0>, EA, EXT>>; + MxBeadDReg<0>, EA, EXT>>; } // Constraints @@ -157,7 +157,7 @@ class MxBiArOp_FMR, !cast("MxOpMode"#TYPE.Size#"EA"#TYPE.RLet), - MxBeadReg<1>, EA, EXT>>; + MxBeadDReg<1>, EA, EXT>>; class MxBiArOp_FMI; - def NAME#"16dd" : MxBiArOp_RFRR_xEA; - def NAME#"32dd" : MxBiArOp_RFRR_xEA; + def NAME#"8dd" : MxBiArOp_RFRR_xEA>; + def NAME#"16dd" : MxBiArOp_RFRR_xEA>; + def NAME#"32dd" : MxBiArOp_RFRR_xEA>; } // isComm @@ -291,7 +291,7 @@ multiclass MxBiArOp_AF; let isCommutable = isComm in - def NAME#"32rr" : MxBiArOp_RFRR_xEA; + def NAME#"32rr" : MxBiArOp_RFRR_xEA>; } // MxBiArOp_AF @@ -313,7 +313,7 @@ class MxBiArOp_RFRRF CMD> [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd, CCR))], MxArithXEncoding, !cast("MxEncSize"#TYPE.Size), - MxBead1Bit<0>, MxBeadReg<2>, MxBeadReg<0>>>; + MxBead1Bit<0>, MxBeadDReg<2>, MxBeadDReg<0>>>; } // Constraints } // Uses, Defs @@ -372,7 +372,7 @@ class MxCmp_RR [(set CCR, (MxCmp TYPE.VT:$lhs, TYPE.VT:$rhs))], MxArithEncoding, !cast("MxOpMode"#TYPE.Size#"dEA"), - MxBeadReg<1>, MxEncEAd_0, MxExtEmpty>>; + MxBeadDReg<1>, MxEncEAd_0, MxExtEmpty>>; class MxCmp_RI : MxInst<(outs), (ins TYPE.IOp:$imm, TYPE.ROp:$reg), @@ -412,7 +412,7 @@ class MxCmp_RM, !cast("MxOpMode"#TYPE.Size#"dEA"), - MxBeadReg<0>, EA, EXT>>; + MxBeadDReg<0>, EA, EXT>>; } // let mayLoad = 1 } // let Defs = [CCR] @@ -474,7 +474,7 @@ def MxExtOpmode_lb : MxBead3Bits<0b111>; /// 0 1 0 0 1 0 0 | OPMODE | 0 0 0 | REG /// --------------------------------------------------- class MxExtEncoding - : MxEncoding, MxBead3Bits<0b000>, OPMODE, + : MxEncoding, MxBead3Bits<0b000>, OPMODE, MxBead3Bits<0b100>, MxBead4Bits<0b0100>>; let Defs = [CCR] in @@ -508,7 +508,7 @@ def MxUDiMuOpmode : MxBead3Bits<0b011>; /// x x x x | REG | OP MODE | MODE | REG /// ---------------------------------------------------- class MxDiMuEncoding - : MxEncoding, CMD, + : MxEncoding, CMD, EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>; let Defs = [CCR] in { diff --git a/lib/Target/M68k/M68kInstrBits.td b/lib/Target/M68k/M68kInstrBits.td index 96d53652093..d97ca50f74a 100644 --- a/lib/Target/M68k/M68kInstrBits.td +++ b/lib/Target/M68k/M68kInstrBits.td @@ -32,7 +32,7 @@ /// ------------+---------+---------+---------+--------- /// 0 0 0 0 | REG | 1 0 0 | MODE | REG /// ------------+---------+---------+---------+--------- -class MxBTSTEnc_R +class MxBTSTEnc_R : MxEncoding, REG, MxBead4Bits<0b0000>, EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>; @@ -52,7 +52,7 @@ let Defs = [CCR] in { class MxBTST_RR : MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.ROp:$bitno), "btst\t$bitno, $dst", [(set CCR, (MxBt TYPE.VT:$dst, TYPE.VT:$bitno))], - MxBTSTEnc_R, MxEncEAd_0, MxExtEmpty>>; + MxBTSTEnc_R, MxEncEAd_0, MxExtEmpty>>; class MxBTST_RI : MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.IOp:$bitno), "btst\t$bitno, $dst", @@ -63,7 +63,7 @@ class MxBTST_MR : MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$bitno), "btst\t$bitno, $dst", [(set CCR, (MxBt (TYPE.Load MEMPat:$dst), TYPE.VT:$bitno))], - MxBTSTEnc_R, EA, EXT>>; + MxBTSTEnc_R, EA, EXT>>; class MxBTST_MI diff --git a/lib/Target/M68k/M68kInstrFormats.td b/lib/Target/M68k/M68kInstrFormats.td index b147537eb32..1d950bd0377 100644 --- a/lib/Target/M68k/M68kInstrFormats.td +++ b/lib/Target/M68k/M68kInstrFormats.td @@ -95,16 +95,17 @@ class MxBead4Bits b> : MxBead<0x4, b{0}, b{1}, b{2}, b{3}>; class MxBeadDAReg o, bit a = 0> : MxBead<0x5, o{0}, o{1}, o{2}, a>; class MxBeadDA o, bit a = 0> : MxBead<0x6, o{0}, o{1}, o{2}, a>; class MxBeadReg o, bit a = 0> : MxBead<0x7, o{0}, o{1}, o{2}, a>; -class MxBead8Disp o, bit a = 0> : MxBead<0x8, o{0}, o{1}, o{2}, a>; +class MxBeadDReg o, bit a = 0> : MxBead<0x8, o{0}, o{1}, o{2}, a>; +class MxBead8Disp o, bit a = 0> : MxBead<0x9, o{0}, o{1}, o{2}, a>; /// Add Immediate to the instruction. 8-bit version is padded with zeros to fit /// the word. -class MxBead8Imm o, bit a = 0> : MxBead<0x9, o{0}, o{1}, o{2}, a>; -class MxBead16Imm o, bit a = 0> : MxBead<0xA, o{0}, o{1}, o{2}, a>; -class MxBead32Imm o, bit a = 0> : MxBead<0xB, o{0}, o{1}, o{2}, a>; +class MxBead8Imm o, bit a = 0> : MxBead<0xA, o{0}, o{1}, o{2}, a>; +class MxBead16Imm o, bit a = 0> : MxBead<0xB, o{0}, o{1}, o{2}, a>; +class MxBead32Imm o, bit a = 0> : MxBead<0xC, o{0}, o{1}, o{2}, a>; /// Encodes an immediate 0-7(alt. 1-8) into 3 bit field -class MxBead3Imm o, bit a = 0> : MxBead<0xC, o{0}, o{1}, o{2}, a>; +class MxBead3Imm o, bit a = 0> : MxBead<0xD, o{0}, o{1}, o{2}, a>; class MxEncoding { // FIXME: Is there a way to factorize the addressing mode suffix (i.e. // 'r', 'd', 'a' etc.) and use something like multiclass to replace? def MxEncEAr_0: MxEncEA, MxBead2Bits<0b00>>; -def MxEncEAd_0: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<0>>; +def MxEncEAd_0: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<0>>; def MxEncEAa_0: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<1>>; def MxEncEAj_0: MxEncEA, MxBead2Bits<0b01>, MxBead1Bit<0>>; def MxEncEAo_0: MxEncEA, MxBead2Bits<0b01>, MxBead1Bit<1>>; @@ -214,7 +215,7 @@ def MxEncEAa_0_reflected : MxEncEA, MxBead3Bits<0b001>>; def MxEncEAr_0_reflected : MxEncEA, MxBead2Bits<0b00>, MxBeadDA<0>>; def MxEncEAr_1: MxEncEA, MxBead2Bits<0b00>>; -def MxEncEAd_1: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<0>>; +def MxEncEAd_1: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<0>>; def MxEncEAa_1: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<1>>; def MxEncEAj_1: MxEncEA, MxBead2Bits<0b01>, MxBead1Bit<0>>; def MxEncEAo_1: MxEncEA, MxBead2Bits<0b01>, MxBead1Bit<1>>; @@ -223,7 +224,7 @@ def MxEncEAp_1: MxEncEA, MxBead2Bits<0b10>, MxBead1Bit<1>>; def MxEncEAf_1: MxEncEA, MxBead2Bits<0b11>, MxBead1Bit<0>>; def MxEncEAr_2: MxEncEA, MxBead2Bits<0b00>>; -def MxEncEAd_2: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<0>>; +def MxEncEAd_2: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<0>>; def MxEncEAa_2: MxEncEA, MxBead2Bits<0b00>, MxBead1Bit<1>>; def MxEncEAj_2: MxEncEA, MxBead2Bits<0b01>, MxBead1Bit<0>>; def MxEncEAo_2: MxEncEA, MxBead2Bits<0b01>, MxBead1Bit<1>>; diff --git a/lib/Target/M68k/M68kInstrShiftRotate.td b/lib/Target/M68k/M68kInstrShiftRotate.td index f777a5d33e2..cab68763807 100644 --- a/lib/Target/M68k/M68kInstrShiftRotate.td +++ b/lib/Target/M68k/M68kInstrShiftRotate.td @@ -38,11 +38,11 @@ def MxROOP_RO : MxBead2Bits<0b11>; /// 1 1 1 0 | REG/IMM | D | SIZE |R/I| OP | REG /// ------------+---------+---+------+---+------+--------- class MxSREncoding_R - : MxEncoding, ROOP, MxBead1Bit<1>, SIZE, DIRECTION, - MxBeadReg<2>, MxBead4Bits<0b1110>>; + : MxEncoding, ROOP, MxBead1Bit<1>, SIZE, DIRECTION, + MxBeadDReg<2>, MxBead4Bits<0b1110>>; class MxSREncoding_I - : MxEncoding, ROOP, MxBead1Bit<0>, SIZE, DIRECTION, + : MxEncoding, ROOP, MxBead1Bit<0>, SIZE, DIRECTION, MxBead3Imm<2, 1>, MxBead4Bits<0b1110>>; // $reg <- $reg op $reg diff --git a/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h b/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h index 36592fda1a9..eac4ded71aa 100644 --- a/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h +++ b/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h @@ -58,11 +58,12 @@ enum { DAReg = 0x5, DA = 0x6, Reg = 0x7, - Disp8 = 0x8, - Imm8 = 0x9, - Imm16 = 0xA, - Imm32 = 0xB, - Imm3 = 0xC, + DReg = 0x8, + Disp8 = 0x9, + Imm8 = 0xA, + Imm16 = 0xB, + Imm32 = 0xC, + Imm3 = 0xD, }; // Ctrl payload diff --git a/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp b/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp index b8579227be1..9708abaadf9 100644 --- a/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp +++ b/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp @@ -121,6 +121,7 @@ unsigned M68kMCCodeEmitter::encodeReg(unsigned ThisByte, uint8_t Bead, Reg = false; DA = true; break; + case M68kBeads::DReg: case M68kBeads::Reg: Reg = true; DA = false; @@ -351,6 +352,7 @@ void M68kMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, break; case M68kBeads::DAReg: case M68kBeads::DA: + case M68kBeads::DReg: case M68kBeads::Reg: Offset += encodeReg(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);