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[Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores.
llvm-svn: 224957
This commit is contained in:
Colin LeMahieu
parent
3e609e8430
commit
51cfbc91d9
@ -122,7 +122,7 @@ void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const {
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if (NumBytes >= ALLOCFRAME_MAX) {
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// Emit allocframe(#0).
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::S2_allocframe)).addImm(0);
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// Subtract offset from frame pointer.
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
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@ -132,7 +132,7 @@ void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const {
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addReg(QRI->getStackRegister()).
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addReg(HEXAGON_RESERVED_REG_1);
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} else {
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::S2_allocframe)).addImm(NumBytes);
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}
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}
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}
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@ -2962,21 +2962,153 @@ def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
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// memh(Rx++#s4:1)=Rt.H
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// Store word.
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// Store predicate.
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let Defs = [R10,R11,D5], hasSideEffects = 0 in
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def STriw_pred : STInst2<(outs),
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(ins MEMri:$addr, PredRegs:$src1),
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"Error; should not emit",
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[]>;
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
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isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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def STriw_pred : STInst<(outs),
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(ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
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".error \"should not emit\"", []>;
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// Allocate stack frame.
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let Defs = [R29, R30], Uses = [R31, R30], hasSideEffects = 0 in {
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def ALLOCFRAME : STInst2<(outs),
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(ins i32imm:$amt),
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"allocframe(#$amt)",
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[]>;
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// S2_allocframe: Allocate stack frame.
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let Defs = [R29, R30], Uses = [R29, R31, R30],
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hasSideEffects = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
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def S2_allocframe: ST0Inst <
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(outs), (ins u11_3Imm:$u11_3),
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"allocframe(#$u11_3)" > {
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bits<14> u11_3;
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let IClass = 0b1010;
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let Inst{27-16} = 0b000010011101;
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let Inst{13-11} = 0b000;
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let Inst{10-0} = u11_3{13-3};
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}
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// S2_storer[bhwdf]_pci: Store byte/half/word/double.
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// S2_storer[bhwdf]_pci -> S2_storerbnew_pci
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let Uses = [CS], isNVStorable = 1 in
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class T_store_pci <string mnemonic, RegisterClass RC,
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Operand Imm, bits<4>MajOp,
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MemAccessSize AlignSize, string RegSrc = "Rt">
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: STInst <(outs IntRegs:$_dst_),
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(ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
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#mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
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[] ,
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"$Rz = $_dst_" > {
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bits<5> Rz;
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bits<7> offset;
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bits<1> Mu;
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bits<5> Rt;
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let accessSize = AlignSize;
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let IClass = 0b1010;
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let Inst{27-25} = 0b100;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = Rz;
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let Inst{13} = Mu;
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let Inst{12-8} = Rt;
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let Inst{7} = 0b0;
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let Inst{6-3} =
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!if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
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!if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
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!if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
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/* ByteAccess */ offset{3-0})));
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let Inst{1} = 0b0;
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}
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let isCodeGenOnly = 0 in {
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def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
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ByteAccess>;
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def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
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HalfWordAccess>;
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def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
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HalfWordAccess, "Rt.h">;
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def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
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WordAccess>;
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def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
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DoubleWordAccess>;
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}
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//===----------------------------------------------------------------------===//
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// Circular stores with auto-increment register
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//===----------------------------------------------------------------------===//
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let Uses = [CS], isNVStorable = 1, isCodeGenOnly = 0 in
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class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
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MemAccessSize AlignSize, string RegSrc = "Rt">
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: STInst <(outs IntRegs:$_dst_),
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(ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
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#mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
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[],
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"$Rz = $_dst_" > {
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bits<5> Rz;
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bits<1> Mu;
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bits<5> Rt;
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let accessSize = AlignSize;
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let IClass = 0b1010;
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let Inst{27-25} = 0b100;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = Rz;
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let Inst{13} = Mu;
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let Inst{12-8} = Rt;
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let Inst{7} = 0b0;
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let Inst{1} = 0b1;
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}
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let isCodeGenOnly = 0 in {
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def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
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def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
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def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
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def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
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def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
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HalfWordAccess, "Rt.h">;
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}
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//===----------------------------------------------------------------------===//
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// Bit-reversed stores with auto-increment register
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0 in
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class T_store_pbr<string mnemonic, RegisterClass RC,
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MemAccessSize addrSize, bits<3> majOp,
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bit isHalf = 0>
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: STInst
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<(outs IntRegs:$_dst_),
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(ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
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#mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
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[], "$Rz = $_dst_" > {
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let accessSize = addrSize;
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bits<5> Rz;
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bits<1> Mu;
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bits<5> src;
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let IClass = 0b1010;
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let Inst{27-24} = 0b1111;
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let Inst{23-21} = majOp;
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let Inst{7} = 0b0;
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let Inst{20-16} = Rz;
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let Inst{13} = Mu;
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let Inst{12-8} = src;
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}
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let isNVStorable = 1, isCodeGenOnly = 0 in {
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let BaseOpcode = "S2_storerb_pbr" in
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def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
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0b000>, NewValueRel;
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let BaseOpcode = "S2_storerh_pbr" in
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def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
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0b010>, NewValueRel;
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let BaseOpcode = "S2_storeri_pbr" in
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def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
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0b100>, NewValueRel;
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}
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let isCodeGenOnly = 0 in {
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def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
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def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
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}
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//===----------------------------------------------------------------------===//
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// ST -
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//===----------------------------------------------------------------------===//
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@ -563,7 +563,7 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore(
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if (PacketSU->getInstr()->getDesc().mayStore() ||
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// if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
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// then we don't need this
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PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
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PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe ||
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PacketSU->getInstr()->getOpcode() == Hexagon::L2_deallocframe)
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return false;
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}
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@ -1115,7 +1115,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
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// first operand is also a reg), first reg is not defined in
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// the same packet.
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if (PacketSU->getInstr()->getDesc().mayStore() ||
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PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
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PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe ||
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// Check #2.
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(!secondRegMatch && NextMI->getOperand(1).isReg() &&
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PacketSU->getInstr()->modifiesRegister(
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@ -1279,7 +1279,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
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// caller's SP. Hence, offset needs to be updated accordingly.
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else if (DepType == SDep::Data
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&& QRI->Subtarget.hasV4TOps()
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&& J->getOpcode() == Hexagon::ALLOCFRAME
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&& J->getOpcode() == Hexagon::S2_allocframe
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&& (I->getOpcode() == Hexagon::S2_storerd_io
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|| I->getOpcode() == Hexagon::S2_storeri_io
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|| I->getOpcode() == Hexagon::S2_storerb_io)
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@ -2,10 +2,16 @@
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0x15 0xd4 0xd1 0xa1
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# CHECK: memd(r17+#168) = r21:20
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0x02 0xf4 0xd1 0xa9
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# CHECK: memd(r17 ++ I:circ(m1)) = r21:20
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0x28 0xf4 0xd1 0xa9
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# CHECK: memd(r17 ++ #40:circ(m1)) = r21:20
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0x28 0xd4 0xd1 0xab
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# CHECK: memd(r17++#40) = r21:20
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0x00 0xf4 0xd1 0xad
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# CHECK: memd(r17++m1) = r21:20
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0x00 0xf4 0xd1 0xaf
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# CHECK: memd(r17 ++ m1:brev) = r21:20
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0xab 0xde 0xd1 0x40
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# CHECK: if (p3) memd(r17+#168) = r31:30
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0xab 0xde 0xd1 0x44
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@ -29,10 +35,16 @@
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0x15 0xd5 0x11 0xa1
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# CHECK: memb(r17+#21) = r21
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0x02 0xf5 0x11 0xa9
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# CHECK: memb(r17 ++ I:circ(m1)) = r21
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0x28 0xf5 0x11 0xa9
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# CHECK: memb(r17 ++ #5:circ(m1)) = r21
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0x28 0xd5 0x11 0xab
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# CHECK: memb(r17++#5) = r21
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0x00 0xf5 0x11 0xad
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# CHECK: memb(r17++m1) = r21
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0x00 0xf5 0x11 0xaf
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# CHECK: memb(r17 ++ m1:brev) = r21
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0xab 0xdf 0x11 0x40
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# CHECK: if (p3) memb(r17+#21) = r31
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0xab 0xdf 0x11 0x44
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@ -58,6 +70,14 @@
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# CHECK: memh(r17+#42) = r31
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0x15 0xdf 0x71 0xa1
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# CHECK: memh(r17+#42) = r31.h
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0x02 0xf5 0x51 0xa9
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# CHECK: memh(r17 ++ I:circ(m1)) = r21
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0x28 0xf5 0x51 0xa9
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# CHECK: memh(r17 ++ #10:circ(m1)) = r21
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0x02 0xf5 0x71 0xa9
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# CHECK: memh(r17 ++ I:circ(m1)) = r21.h
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0x28 0xf5 0x71 0xa9
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# CHECK: memh(r17 ++ #10:circ(m1)) = r21.h
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0x28 0xd5 0x51 0xab
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# CHECK: memh(r17++#10) = r21
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0x28 0xd5 0x71 0xab
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@ -66,6 +86,10 @@
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# CHECK: memh(r17++m1) = r21
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0x00 0xf5 0x71 0xad
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# CHECK: memh(r17++m1) = r21.h
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0x00 0xf5 0x51 0xaf
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# CHECK: memh(r17 ++ m1:brev) = r21
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0x00 0xf5 0x71 0xaf
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# CHECK: memh(r17 ++ m1:brev) = r21.h
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0xfb 0xd5 0x51 0x40
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# CHECK: if (p3) memh(r17+#62) = r21
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0xfb 0xd5 0x71 0x40
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@ -109,10 +133,16 @@
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0x15 0xdf 0x91 0xa1
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# CHECK: memw(r17+#84) = r31
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0x02 0xf5 0x91 0xa9
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# CHECK: memw(r17 ++ I:circ(m1)) = r21
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0x28 0xf5 0x91 0xa9
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# CHECK: memw(r17 ++ #20:circ(m1)) = r21
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0x28 0xd5 0x91 0xab
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# CHECK: memw(r17++#20) = r21
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0x00 0xf5 0x91 0xad
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# CHECK: memw(r17++m1) = r21
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0x00 0xf5 0x91 0xaf
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# CHECK: memw(r17 ++ m1:brev) = r21
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0xab 0xdf 0x91 0x40
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# CHECK: if (p3) memw(r17+#84) = r31
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0xab 0xdf 0x91 0x44
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@ -132,4 +162,7 @@
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# CHECK-NEXT: if (!p3.new) memw(r17++#20) = r21
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0x03 0x40 0x45 0x85 0xab 0xf5 0x91 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) memw(r17++#20) = r21
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# CHECK-NEXT: if (p3.new) memw(r17++#20) = r21
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0x1f 0xc0 0x9d 0xa0
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# CHECK: allocframe(#248)
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