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[SLPVectorizer][X86] Add mul/and/or/xor unrolled reduction tests
We miss arithmetic reduction for everything but Add/FAdd (I assume because that's the only cases which x86 has horizontal ops for.....) llvm-svn: 344849
This commit is contained in:
Simon Pilgrim
parent
944c3c14c4
commit
51d177a471
@ -3,19 +3,19 @@
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug < %s 2>&1 | FileCheck --check-prefix=SSE2 %s
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; REQUIRES: asserts
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; int test(unsigned int *p) {
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; int sum = 0;
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; int test_add(unsigned int *p) {
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; int result = 0;
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; for (int i = 0; i < 8; i++)
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; sum += p[i];
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; return sum;
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; result += p[i];
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; return result;
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; }
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; Vector cost is 5, Scalar cost is 7
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; CHECK: Adding cost -2 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
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; Vector cost is 11, Scalar cost is 7
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; SSE2: Adding cost 4 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
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define i32 @test(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test(
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define i32 @test_add(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test_add(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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@ -42,7 +42,7 @@ define i32 @test(i32* nocapture readonly %p) {
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; CHECK-NEXT: [[MUL_714:%.*]] = add i32 undef, [[MUL_613]]
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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; SSE2-LABEL: @test(
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; SSE2-LABEL: @test_add(
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; SSE2-NEXT: entry:
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; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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@ -94,3 +94,347 @@ entry:
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%mul.714 = add i32 %7, %mul.613
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ret i32 %mul.714
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}
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; int test_mul(unsigned int *p) {
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; int result = 0;
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; for (int i = 0; i < 8; i++)
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; result *= p[i];
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; return result;
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; }
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define i32 @test_mul(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test_mul(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; CHECK-NEXT: [[MUL_18:%.*]] = mul i32 [[TMP1]], [[TMP0]]
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; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; CHECK-NEXT: [[MUL_29:%.*]] = mul i32 [[TMP2]], [[MUL_18]]
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; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; CHECK-NEXT: [[MUL_310:%.*]] = mul i32 [[TMP3]], [[MUL_29]]
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; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; CHECK-NEXT: [[MUL_411:%.*]] = mul i32 [[TMP4]], [[MUL_310]]
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; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; CHECK-NEXT: [[MUL_512:%.*]] = mul i32 [[TMP5]], [[MUL_411]]
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; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
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; CHECK-NEXT: [[MUL_613:%.*]] = mul i32 [[TMP6]], [[MUL_512]]
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; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
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; CHECK-NEXT: [[MUL_714:%.*]] = mul i32 [[TMP7]], [[MUL_613]]
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; CHECK-NEXT: ret i32 [[MUL_714]]
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;
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; SSE2-LABEL: @test_mul(
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; SSE2-NEXT: entry:
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; SSE2-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; SSE2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; SSE2-NEXT: [[MUL_18:%.*]] = mul i32 [[TMP1]], [[TMP0]]
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; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; SSE2-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; SSE2-NEXT: [[MUL_29:%.*]] = mul i32 [[TMP2]], [[MUL_18]]
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; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; SSE2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; SSE2-NEXT: [[MUL_310:%.*]] = mul i32 [[TMP3]], [[MUL_29]]
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; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; SSE2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; SSE2-NEXT: [[MUL_411:%.*]] = mul i32 [[TMP4]], [[MUL_310]]
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; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; SSE2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; SSE2-NEXT: [[MUL_512:%.*]] = mul i32 [[TMP5]], [[MUL_411]]
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; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; SSE2-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
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; SSE2-NEXT: [[MUL_613:%.*]] = mul i32 [[TMP6]], [[MUL_512]]
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; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; SSE2-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
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; SSE2-NEXT: [[MUL_714:%.*]] = mul i32 [[TMP7]], [[MUL_613]]
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; SSE2-NEXT: ret i32 [[MUL_714]]
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;
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entry:
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%0 = load i32, i32* %p, align 4
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%arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1
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%1 = load i32, i32* %arrayidx.1, align 4
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%mul.18 = mul i32 %1, %0
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%arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2
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%2 = load i32, i32* %arrayidx.2, align 4
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%mul.29 = mul i32 %2, %mul.18
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%arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3
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%3 = load i32, i32* %arrayidx.3, align 4
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%mul.310 = mul i32 %3, %mul.29
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%arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4
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%4 = load i32, i32* %arrayidx.4, align 4
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%mul.411 = mul i32 %4, %mul.310
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%arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5
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%5 = load i32, i32* %arrayidx.5, align 4
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%mul.512 = mul i32 %5, %mul.411
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%arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6
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%6 = load i32, i32* %arrayidx.6, align 4
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%mul.613 = mul i32 %6, %mul.512
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%arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7
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%7 = load i32, i32* %arrayidx.7, align 4
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%mul.714 = mul i32 %7, %mul.613
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ret i32 %mul.714
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}
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; int test_and(unsigned int *p) {
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; int result = 0;
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; for (int i = 0; i < 8; i++)
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; result &= p[i];
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; return result;
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; }
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define i32 @test_and(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test_and(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; CHECK-NEXT: [[MUL_18:%.*]] = and i32 [[TMP1]], [[TMP0]]
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; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; CHECK-NEXT: [[MUL_29:%.*]] = and i32 [[TMP2]], [[MUL_18]]
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; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; CHECK-NEXT: [[MUL_310:%.*]] = and i32 [[TMP3]], [[MUL_29]]
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; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; CHECK-NEXT: [[MUL_411:%.*]] = and i32 [[TMP4]], [[MUL_310]]
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; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; CHECK-NEXT: [[MUL_512:%.*]] = and i32 [[TMP5]], [[MUL_411]]
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; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
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; CHECK-NEXT: [[MUL_613:%.*]] = and i32 [[TMP6]], [[MUL_512]]
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; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
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; CHECK-NEXT: [[MUL_714:%.*]] = and i32 [[TMP7]], [[MUL_613]]
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; CHECK-NEXT: ret i32 [[MUL_714]]
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;
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; SSE2-LABEL: @test_and(
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; SSE2-NEXT: entry:
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; SSE2-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; SSE2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; SSE2-NEXT: [[MUL_18:%.*]] = and i32 [[TMP1]], [[TMP0]]
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; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; SSE2-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; SSE2-NEXT: [[MUL_29:%.*]] = and i32 [[TMP2]], [[MUL_18]]
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; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; SSE2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; SSE2-NEXT: [[MUL_310:%.*]] = and i32 [[TMP3]], [[MUL_29]]
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; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; SSE2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; SSE2-NEXT: [[MUL_411:%.*]] = and i32 [[TMP4]], [[MUL_310]]
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; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; SSE2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; SSE2-NEXT: [[MUL_512:%.*]] = and i32 [[TMP5]], [[MUL_411]]
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; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; SSE2-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
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; SSE2-NEXT: [[MUL_613:%.*]] = and i32 [[TMP6]], [[MUL_512]]
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; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; SSE2-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
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; SSE2-NEXT: [[MUL_714:%.*]] = and i32 [[TMP7]], [[MUL_613]]
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; SSE2-NEXT: ret i32 [[MUL_714]]
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;
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entry:
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%0 = load i32, i32* %p, align 4
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%arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1
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%1 = load i32, i32* %arrayidx.1, align 4
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%mul.18 = and i32 %1, %0
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%arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2
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%2 = load i32, i32* %arrayidx.2, align 4
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%mul.29 = and i32 %2, %mul.18
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%arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3
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%3 = load i32, i32* %arrayidx.3, align 4
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%mul.310 = and i32 %3, %mul.29
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%arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4
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%4 = load i32, i32* %arrayidx.4, align 4
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%mul.411 = and i32 %4, %mul.310
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%arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5
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%5 = load i32, i32* %arrayidx.5, align 4
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%mul.512 = and i32 %5, %mul.411
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%arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6
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%6 = load i32, i32* %arrayidx.6, align 4
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%mul.613 = and i32 %6, %mul.512
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%arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7
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%7 = load i32, i32* %arrayidx.7, align 4
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%mul.714 = and i32 %7, %mul.613
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ret i32 %mul.714
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}
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; int test_or(unsigned int *p) {
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; int result = 0;
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; for (int i = 0; i < 8; i++)
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; result |= p[i];
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; return result;
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; }
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define i32 @test_or(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test_or(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; CHECK-NEXT: [[MUL_18:%.*]] = or i32 [[TMP1]], [[TMP0]]
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; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; CHECK-NEXT: [[MUL_29:%.*]] = or i32 [[TMP2]], [[MUL_18]]
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; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; CHECK-NEXT: [[MUL_310:%.*]] = or i32 [[TMP3]], [[MUL_29]]
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; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; CHECK-NEXT: [[MUL_411:%.*]] = or i32 [[TMP4]], [[MUL_310]]
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; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; CHECK-NEXT: [[MUL_512:%.*]] = or i32 [[TMP5]], [[MUL_411]]
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; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
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; CHECK-NEXT: [[MUL_613:%.*]] = or i32 [[TMP6]], [[MUL_512]]
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; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
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; CHECK-NEXT: [[MUL_714:%.*]] = or i32 [[TMP7]], [[MUL_613]]
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; CHECK-NEXT: ret i32 [[MUL_714]]
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;
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; SSE2-LABEL: @test_or(
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; SSE2-NEXT: entry:
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; SSE2-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; SSE2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; SSE2-NEXT: [[MUL_18:%.*]] = or i32 [[TMP1]], [[TMP0]]
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; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; SSE2-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; SSE2-NEXT: [[MUL_29:%.*]] = or i32 [[TMP2]], [[MUL_18]]
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; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; SSE2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; SSE2-NEXT: [[MUL_310:%.*]] = or i32 [[TMP3]], [[MUL_29]]
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; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; SSE2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; SSE2-NEXT: [[MUL_411:%.*]] = or i32 [[TMP4]], [[MUL_310]]
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; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; SSE2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; SSE2-NEXT: [[MUL_512:%.*]] = or i32 [[TMP5]], [[MUL_411]]
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; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; SSE2-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
|
||||
; SSE2-NEXT: [[MUL_613:%.*]] = or i32 [[TMP6]], [[MUL_512]]
|
||||
; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; SSE2-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
|
||||
; SSE2-NEXT: [[MUL_714:%.*]] = or i32 [[TMP7]], [[MUL_613]]
|
||||
; SSE2-NEXT: ret i32 [[MUL_714]]
|
||||
;
|
||||
entry:
|
||||
%0 = load i32, i32* %p, align 4
|
||||
%arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1
|
||||
%1 = load i32, i32* %arrayidx.1, align 4
|
||||
%mul.18 = or i32 %1, %0
|
||||
%arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2
|
||||
%2 = load i32, i32* %arrayidx.2, align 4
|
||||
%mul.29 = or i32 %2, %mul.18
|
||||
%arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3
|
||||
%3 = load i32, i32* %arrayidx.3, align 4
|
||||
%mul.310 = or i32 %3, %mul.29
|
||||
%arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4
|
||||
%4 = load i32, i32* %arrayidx.4, align 4
|
||||
%mul.411 = or i32 %4, %mul.310
|
||||
%arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5
|
||||
%5 = load i32, i32* %arrayidx.5, align 4
|
||||
%mul.512 = or i32 %5, %mul.411
|
||||
%arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6
|
||||
%6 = load i32, i32* %arrayidx.6, align 4
|
||||
%mul.613 = or i32 %6, %mul.512
|
||||
%arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7
|
||||
%7 = load i32, i32* %arrayidx.7, align 4
|
||||
%mul.714 = or i32 %7, %mul.613
|
||||
ret i32 %mul.714
|
||||
}
|
||||
|
||||
; int test_xor(unsigned int *p) {
|
||||
; int result = 0;
|
||||
; for (int i = 0; i < 8; i++)
|
||||
; result ^= p[i];
|
||||
; return result;
|
||||
; }
|
||||
|
||||
define i32 @test_xor(i32* nocapture readonly %p) {
|
||||
; CHECK-LABEL: @test_xor(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
|
||||
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
|
||||
; CHECK-NEXT: [[MUL_18:%.*]] = xor i32 [[TMP1]], [[TMP0]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
|
||||
; CHECK-NEXT: [[MUL_29:%.*]] = xor i32 [[TMP2]], [[MUL_18]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
|
||||
; CHECK-NEXT: [[MUL_310:%.*]] = xor i32 [[TMP3]], [[MUL_29]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
|
||||
; CHECK-NEXT: [[MUL_411:%.*]] = xor i32 [[TMP4]], [[MUL_310]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
|
||||
; CHECK-NEXT: [[MUL_512:%.*]] = xor i32 [[TMP5]], [[MUL_411]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
|
||||
; CHECK-NEXT: [[MUL_613:%.*]] = xor i32 [[TMP6]], [[MUL_512]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
|
||||
; CHECK-NEXT: [[MUL_714:%.*]] = xor i32 [[TMP7]], [[MUL_613]]
|
||||
; CHECK-NEXT: ret i32 [[MUL_714]]
|
||||
;
|
||||
; SSE2-LABEL: @test_xor(
|
||||
; SSE2-NEXT: entry:
|
||||
; SSE2-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
|
||||
; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
|
||||
; SSE2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
|
||||
; SSE2-NEXT: [[MUL_18:%.*]] = xor i32 [[TMP1]], [[TMP0]]
|
||||
; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; SSE2-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
|
||||
; SSE2-NEXT: [[MUL_29:%.*]] = xor i32 [[TMP2]], [[MUL_18]]
|
||||
; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; SSE2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
|
||||
; SSE2-NEXT: [[MUL_310:%.*]] = xor i32 [[TMP3]], [[MUL_29]]
|
||||
; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; SSE2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
|
||||
; SSE2-NEXT: [[MUL_411:%.*]] = xor i32 [[TMP4]], [[MUL_310]]
|
||||
; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; SSE2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
|
||||
; SSE2-NEXT: [[MUL_512:%.*]] = xor i32 [[TMP5]], [[MUL_411]]
|
||||
; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; SSE2-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
|
||||
; SSE2-NEXT: [[MUL_613:%.*]] = xor i32 [[TMP6]], [[MUL_512]]
|
||||
; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; SSE2-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
|
||||
; SSE2-NEXT: [[MUL_714:%.*]] = xor i32 [[TMP7]], [[MUL_613]]
|
||||
; SSE2-NEXT: ret i32 [[MUL_714]]
|
||||
;
|
||||
entry:
|
||||
%0 = load i32, i32* %p, align 4
|
||||
%arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1
|
||||
%1 = load i32, i32* %arrayidx.1, align 4
|
||||
%mul.18 = xor i32 %1, %0
|
||||
%arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2
|
||||
%2 = load i32, i32* %arrayidx.2, align 4
|
||||
%mul.29 = xor i32 %2, %mul.18
|
||||
%arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3
|
||||
%3 = load i32, i32* %arrayidx.3, align 4
|
||||
%mul.310 = xor i32 %3, %mul.29
|
||||
%arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4
|
||||
%4 = load i32, i32* %arrayidx.4, align 4
|
||||
%mul.411 = xor i32 %4, %mul.310
|
||||
%arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5
|
||||
%5 = load i32, i32* %arrayidx.5, align 4
|
||||
%mul.512 = xor i32 %5, %mul.411
|
||||
%arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6
|
||||
%6 = load i32, i32* %arrayidx.6, align 4
|
||||
%mul.613 = xor i32 %6, %mul.512
|
||||
%arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7
|
||||
%7 = load i32, i32* %arrayidx.7, align 4
|
||||
%mul.714 = xor i32 %7, %mul.613
|
||||
ret i32 %mul.714
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user