From 51f3472bbdcae7e9758f7fd8cdcbb7fc1948e972 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Sun, 11 Jul 2021 12:31:02 -0700
Subject: [PATCH] [RISCV] Add tests for suboptimal handling of negative
 constants for i32 uaddo/usubo on RV64. NFC

We end up zero extending constants when we promote to i64. We
should sign extend instead to allow use of addiw or improve
constant materialization.
---
 test/CodeGen/RISCV/xaluo.ll | 688 ++++++++++++++++++++++--------------
 1 file changed, 418 insertions(+), 270 deletions(-)

diff --git a/test/CodeGen/RISCV/xaluo.ll b/test/CodeGen/RISCV/xaluo.ll
index 707d1621d6e..1fd89bde766 100644
--- a/test/CodeGen/RISCV/xaluo.ll
+++ b/test/CodeGen/RISCV/xaluo.ll
@@ -390,6 +390,54 @@ entry:
   ret i1 %obit
 }
 
+define zeroext i1 @uaddo.i32.constant(i32 %v1, i32* %res) {
+; RV32-LABEL: uaddo.i32.constant:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    addi a2, a0, -2
+; RV32-NEXT:    sltu a0, a2, a0
+; RV32-NEXT:    sw a2, 0(a1)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: uaddo.i32.constant:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi a2, zero, 1
+; RV64-NEXT:    slli a2, a2, 32
+; RV64-NEXT:    addi a3, a2, -2
+; RV64-NEXT:    addw a2, a0, a3
+; RV64-NEXT:    sext.w a4, a0
+; RV64-NEXT:    sltu a2, a2, a4
+; RV64-NEXT:    add a0, a0, a3
+; RV64-NEXT:    sw a0, 0(a1)
+; RV64-NEXT:    mv a0, a2
+; RV64-NEXT:    ret
+;
+; RV32ZBA-LABEL: uaddo.i32.constant:
+; RV32ZBA:       # %bb.0: # %entry
+; RV32ZBA-NEXT:    addi a2, a0, -2
+; RV32ZBA-NEXT:    sltu a0, a2, a0
+; RV32ZBA-NEXT:    sw a2, 0(a1)
+; RV32ZBA-NEXT:    ret
+;
+; RV64ZBA-LABEL: uaddo.i32.constant:
+; RV64ZBA:       # %bb.0: # %entry
+; RV64ZBA-NEXT:    addi a2, zero, 1
+; RV64ZBA-NEXT:    slli a2, a2, 32
+; RV64ZBA-NEXT:    addi a3, a2, -2
+; RV64ZBA-NEXT:    addw a2, a0, a3
+; RV64ZBA-NEXT:    sext.w a4, a0
+; RV64ZBA-NEXT:    sltu a2, a2, a4
+; RV64ZBA-NEXT:    add a0, a0, a3
+; RV64ZBA-NEXT:    sw a0, 0(a1)
+; RV64ZBA-NEXT:    mv a0, a2
+; RV64ZBA-NEXT:    ret
+entry:
+  %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 -2)
+  %val = extractvalue {i32, i1} %t, 0
+  %obit = extractvalue {i32, i1} %t, 1
+  store i32 %val, i32* %res
+  ret i1 %obit
+}
+
 define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
 ; RV32-LABEL: uaddo.i64:
 ; RV32:       # %bb.0: # %entry
@@ -397,10 +445,10 @@ define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a3, a3, a0
-; RV32-NEXT:    beq a3, a1, .LBB8_2
+; RV32-NEXT:    beq a3, a1, .LBB9_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a3, a1
-; RV32-NEXT:  .LBB8_2: # %entry
+; RV32-NEXT:  .LBB9_2: # %entry
 ; RV32-NEXT:    sw a2, 0(a4)
 ; RV32-NEXT:    sw a3, 4(a4)
 ; RV32-NEXT:    ret
@@ -418,10 +466,10 @@ define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a3, a3, a0
-; RV32ZBA-NEXT:    beq a3, a1, .LBB8_2
+; RV32ZBA-NEXT:    beq a3, a1, .LBB9_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a3, a1
-; RV32ZBA-NEXT:  .LBB8_2: # %entry
+; RV32ZBA-NEXT:  .LBB9_2: # %entry
 ; RV32ZBA-NEXT:    sw a2, 0(a4)
 ; RV32ZBA-NEXT:    sw a3, 4(a4)
 ; RV32ZBA-NEXT:    ret
@@ -628,6 +676,106 @@ entry:
   ret i1 %obit
 }
 
+define zeroext i1 @usubo.i32.constant.rhs(i32 %v1, i32* %res) {
+; RV32-LABEL: usubo.i32.constant.rhs:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    addi a2, a0, 2
+; RV32-NEXT:    sltu a0, a0, a2
+; RV32-NEXT:    sw a2, 0(a1)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: usubo.i32.constant.rhs:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi a2, zero, -1
+; RV64-NEXT:    slli a2, a2, 32
+; RV64-NEXT:    addi a3, a2, 2
+; RV64-NEXT:    addw a2, a0, a3
+; RV64-NEXT:    sext.w a4, a0
+; RV64-NEXT:    sltu a2, a4, a2
+; RV64-NEXT:    add a0, a0, a3
+; RV64-NEXT:    sw a0, 0(a1)
+; RV64-NEXT:    mv a0, a2
+; RV64-NEXT:    ret
+;
+; RV32ZBA-LABEL: usubo.i32.constant.rhs:
+; RV32ZBA:       # %bb.0: # %entry
+; RV32ZBA-NEXT:    addi a2, a0, 2
+; RV32ZBA-NEXT:    sltu a0, a0, a2
+; RV32ZBA-NEXT:    sw a2, 0(a1)
+; RV32ZBA-NEXT:    ret
+;
+; RV64ZBA-LABEL: usubo.i32.constant.rhs:
+; RV64ZBA:       # %bb.0: # %entry
+; RV64ZBA-NEXT:    addi a2, zero, -1
+; RV64ZBA-NEXT:    slli a2, a2, 32
+; RV64ZBA-NEXT:    addi a3, a2, 2
+; RV64ZBA-NEXT:    addw a2, a0, a3
+; RV64ZBA-NEXT:    sext.w a4, a0
+; RV64ZBA-NEXT:    sltu a2, a4, a2
+; RV64ZBA-NEXT:    add a0, a0, a3
+; RV64ZBA-NEXT:    sw a0, 0(a1)
+; RV64ZBA-NEXT:    mv a0, a2
+; RV64ZBA-NEXT:    ret
+entry:
+  %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 -2)
+  %val = extractvalue {i32, i1} %t, 0
+  %obit = extractvalue {i32, i1} %t, 1
+  store i32 %val, i32* %res
+  ret i1 %obit
+}
+
+define zeroext i1 @usubo.i32.constant.lhs(i32 %v1, i32* %res) {
+; RV32-LABEL: usubo.i32.constant.lhs:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    addi a2, zero, -2
+; RV32-NEXT:    sub a2, a2, a0
+; RV32-NEXT:    addi a0, a2, 1
+; RV32-NEXT:    seqz a0, a0
+; RV32-NEXT:    sw a2, 0(a1)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: usubo.i32.constant.lhs:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi a2, zero, 1
+; RV64-NEXT:    slli a2, a2, 32
+; RV64-NEXT:    addi a3, a2, -2
+; RV64-NEXT:    subw a2, a3, a0
+; RV64-NEXT:    addi a2, a2, 1
+; RV64-NEXT:    seqz a2, a2
+; RV64-NEXT:    sub a0, a3, a0
+; RV64-NEXT:    sw a0, 0(a1)
+; RV64-NEXT:    mv a0, a2
+; RV64-NEXT:    ret
+;
+; RV32ZBA-LABEL: usubo.i32.constant.lhs:
+; RV32ZBA:       # %bb.0: # %entry
+; RV32ZBA-NEXT:    addi a2, zero, -2
+; RV32ZBA-NEXT:    sub a2, a2, a0
+; RV32ZBA-NEXT:    addi a0, a2, 1
+; RV32ZBA-NEXT:    seqz a0, a0
+; RV32ZBA-NEXT:    sw a2, 0(a1)
+; RV32ZBA-NEXT:    ret
+;
+; RV64ZBA-LABEL: usubo.i32.constant.lhs:
+; RV64ZBA:       # %bb.0: # %entry
+; RV64ZBA-NEXT:    addi a2, zero, 1
+; RV64ZBA-NEXT:    slli a2, a2, 32
+; RV64ZBA-NEXT:    addi a3, a2, -2
+; RV64ZBA-NEXT:    subw a2, a3, a0
+; RV64ZBA-NEXT:    addi a2, a2, 1
+; RV64ZBA-NEXT:    seqz a2, a2
+; RV64ZBA-NEXT:    sub a0, a3, a0
+; RV64ZBA-NEXT:    sw a0, 0(a1)
+; RV64ZBA-NEXT:    mv a0, a2
+; RV64ZBA-NEXT:    ret
+entry:
+  %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 -2, i32 %v1)
+  %val = extractvalue {i32, i1} %t, 0
+  %obit = extractvalue {i32, i1} %t, 1
+  store i32 %val, i32* %res
+  ret i1 %obit
+}
+
 define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
 ; RV32-LABEL: usubo.i64:
 ; RV32:       # %bb.0: # %entry
@@ -635,13 +783,13 @@ define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
 ; RV32-NEXT:    sub a3, a1, a3
 ; RV32-NEXT:    sub a3, a3, a5
 ; RV32-NEXT:    sub a2, a0, a2
-; RV32-NEXT:    beq a3, a1, .LBB13_2
+; RV32-NEXT:    beq a3, a1, .LBB16_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
-; RV32-NEXT:    j .LBB13_3
-; RV32-NEXT:  .LBB13_2:
+; RV32-NEXT:    j .LBB16_3
+; RV32-NEXT:  .LBB16_2:
 ; RV32-NEXT:    sltu a0, a0, a2
-; RV32-NEXT:  .LBB13_3: # %entry
+; RV32-NEXT:  .LBB16_3: # %entry
 ; RV32-NEXT:    sw a2, 0(a4)
 ; RV32-NEXT:    sw a3, 4(a4)
 ; RV32-NEXT:    ret
@@ -659,13 +807,13 @@ define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
 ; RV32ZBA-NEXT:    sub a3, a1, a3
 ; RV32ZBA-NEXT:    sub a3, a3, a5
 ; RV32ZBA-NEXT:    sub a2, a0, a2
-; RV32ZBA-NEXT:    beq a3, a1, .LBB13_2
+; RV32ZBA-NEXT:    beq a3, a1, .LBB16_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
-; RV32ZBA-NEXT:    j .LBB13_3
-; RV32ZBA-NEXT:  .LBB13_2:
+; RV32ZBA-NEXT:    j .LBB16_3
+; RV32ZBA-NEXT:  .LBB16_2:
 ; RV32ZBA-NEXT:    sltu a0, a0, a2
-; RV32ZBA-NEXT:  .LBB13_3: # %entry
+; RV32ZBA-NEXT:  .LBB16_3: # %entry
 ; RV32ZBA-NEXT:    sw a2, 0(a4)
 ; RV32ZBA-NEXT:    sw a3, 4(a4)
 ; RV32ZBA-NEXT:    ret
@@ -1224,10 +1372,10 @@ define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    slt a2, a2, a0
 ; RV32-NEXT:    slti a3, a1, 0
-; RV32-NEXT:    bne a3, a2, .LBB23_2
+; RV32-NEXT:    bne a3, a2, .LBB26_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB23_2: # %entry
+; RV32-NEXT:  .LBB26_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.select.i32:
@@ -1236,10 +1384,10 @@ define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
 ; RV64-NEXT:    sext.w a3, a0
 ; RV64-NEXT:    add a4, a3, a2
 ; RV64-NEXT:    addw a2, a3, a2
-; RV64-NEXT:    bne a2, a4, .LBB23_2
+; RV64-NEXT:    bne a2, a4, .LBB26_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB23_2: # %entry
+; RV64-NEXT:  .LBB26_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.select.i32:
@@ -1247,10 +1395,10 @@ define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
 ; RV32ZBA-NEXT:    add a2, a0, a1
 ; RV32ZBA-NEXT:    slt a2, a2, a0
 ; RV32ZBA-NEXT:    slti a3, a1, 0
-; RV32ZBA-NEXT:    bne a3, a2, .LBB23_2
+; RV32ZBA-NEXT:    bne a3, a2, .LBB26_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB23_2: # %entry
+; RV32ZBA-NEXT:  .LBB26_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: saddo.select.i32:
@@ -1259,10 +1407,10 @@ define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA-NEXT:    sext.w a3, a0
 ; RV64ZBA-NEXT:    add a4, a3, a2
 ; RV64ZBA-NEXT:    addw a2, a3, a2
-; RV64ZBA-NEXT:    bne a2, a4, .LBB23_2
+; RV64ZBA-NEXT:    bne a2, a4, .LBB26_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB23_2: # %entry
+; RV64ZBA-NEXT:  .LBB26_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1327,11 +1475,11 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    xor a5, a1, a3
 ; RV32-NEXT:    not a5, a5
 ; RV32-NEXT:    and a4, a5, a4
-; RV32-NEXT:    bltz a4, .LBB25_2
+; RV32-NEXT:    bltz a4, .LBB28_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB25_2: # %entry
+; RV32-NEXT:  .LBB28_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.select.i64:
@@ -1339,10 +1487,10 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    slt a2, a2, a0
 ; RV64-NEXT:    slti a3, a1, 0
-; RV64-NEXT:    bne a3, a2, .LBB25_2
+; RV64-NEXT:    bne a3, a2, .LBB28_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB25_2: # %entry
+; RV64-NEXT:  .LBB28_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.select.i64:
@@ -1355,11 +1503,11 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    xor a5, a1, a3
 ; RV32ZBA-NEXT:    not a5, a5
 ; RV32ZBA-NEXT:    and a4, a5, a4
-; RV32ZBA-NEXT:    bltz a4, .LBB25_2
+; RV32ZBA-NEXT:    bltz a4, .LBB28_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB25_2: # %entry
+; RV32ZBA-NEXT:  .LBB28_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: saddo.select.i64:
@@ -1367,10 +1515,10 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
 ; RV64ZBA-NEXT:    add a2, a0, a1
 ; RV64ZBA-NEXT:    slt a2, a2, a0
 ; RV64ZBA-NEXT:    slti a3, a1, 0
-; RV64ZBA-NEXT:    bne a3, a2, .LBB25_2
+; RV64ZBA-NEXT:    bne a3, a2, .LBB28_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB25_2: # %entry
+; RV64ZBA-NEXT:  .LBB28_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
@@ -1436,39 +1584,39 @@ define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: uaddo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a2, a0, a1
-; RV32-NEXT:    bltu a2, a0, .LBB27_2
+; RV32-NEXT:    bltu a2, a0, .LBB30_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB27_2: # %entry
+; RV32-NEXT:  .LBB30_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addw a2, a0, a1
 ; RV64-NEXT:    sext.w a3, a0
-; RV64-NEXT:    bltu a2, a3, .LBB27_2
+; RV64-NEXT:    bltu a2, a3, .LBB30_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB27_2: # %entry
+; RV64-NEXT:  .LBB30_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a2, a0, a1
-; RV32ZBA-NEXT:    bltu a2, a0, .LBB27_2
+; RV32ZBA-NEXT:    bltu a2, a0, .LBB30_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB27_2: # %entry
+; RV32ZBA-NEXT:  .LBB30_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    addw a2, a0, a1
 ; RV64ZBA-NEXT:    sext.w a3, a0
-; RV64ZBA-NEXT:    bltu a2, a3, .LBB27_2
+; RV64ZBA-NEXT:    bltu a2, a3, .LBB30_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB27_2: # %entry
+; RV64ZBA-NEXT:  .LBB30_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1521,15 +1669,15 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    add a4, a0, a2
 ; RV32-NEXT:    sltu a4, a4, a0
 ; RV32-NEXT:    add a5, a5, a4
-; RV32-NEXT:    bne a5, a1, .LBB29_3
+; RV32-NEXT:    bne a5, a1, .LBB32_3
 ; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    beqz a4, .LBB29_4
-; RV32-NEXT:  .LBB29_2: # %entry
+; RV32-NEXT:    beqz a4, .LBB32_4
+; RV32-NEXT:  .LBB32_2: # %entry
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB29_3: # %entry
+; RV32-NEXT:  .LBB32_3: # %entry
 ; RV32-NEXT:    sltu a4, a5, a1
-; RV32-NEXT:    bnez a4, .LBB29_2
-; RV32-NEXT:  .LBB29_4: # %entry
+; RV32-NEXT:    bnez a4, .LBB32_2
+; RV32-NEXT:  .LBB32_4: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:    ret
@@ -1537,10 +1685,10 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 ; RV64-LABEL: uaddo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
-; RV64-NEXT:    bltu a2, a0, .LBB29_2
+; RV64-NEXT:    bltu a2, a0, .LBB32_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB29_2: # %entry
+; RV64-NEXT:  .LBB32_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.select.i64:
@@ -1549,15 +1697,15 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    add a4, a0, a2
 ; RV32ZBA-NEXT:    sltu a4, a4, a0
 ; RV32ZBA-NEXT:    add a5, a5, a4
-; RV32ZBA-NEXT:    bne a5, a1, .LBB29_3
+; RV32ZBA-NEXT:    bne a5, a1, .LBB32_3
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
-; RV32ZBA-NEXT:    beqz a4, .LBB29_4
-; RV32ZBA-NEXT:  .LBB29_2: # %entry
+; RV32ZBA-NEXT:    beqz a4, .LBB32_4
+; RV32ZBA-NEXT:  .LBB32_2: # %entry
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB29_3: # %entry
+; RV32ZBA-NEXT:  .LBB32_3: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a5, a1
-; RV32ZBA-NEXT:    bnez a4, .LBB29_2
-; RV32ZBA-NEXT:  .LBB29_4: # %entry
+; RV32ZBA-NEXT:    bnez a4, .LBB32_2
+; RV32ZBA-NEXT:  .LBB32_4: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
 ; RV32ZBA-NEXT:    ret
@@ -1565,10 +1713,10 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 ; RV64ZBA-LABEL: uaddo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a2, a0, a1
-; RV64ZBA-NEXT:    bltu a2, a0, .LBB29_2
+; RV64ZBA-NEXT:    bltu a2, a0, .LBB32_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB29_2: # %entry
+; RV64ZBA-NEXT:  .LBB32_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
@@ -1584,10 +1732,10 @@ define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a2, a3, a0
-; RV32-NEXT:    beq a2, a1, .LBB30_2
+; RV32-NEXT:    beq a2, a1, .LBB33_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
-; RV32-NEXT:  .LBB30_2: # %entry
+; RV32-NEXT:  .LBB33_2: # %entry
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
@@ -1604,10 +1752,10 @@ define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a2, a3, a0
-; RV32ZBA-NEXT:    beq a2, a1, .LBB30_2
+; RV32ZBA-NEXT:    beq a2, a1, .LBB33_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
-; RV32ZBA-NEXT:  .LBB30_2: # %entry
+; RV32ZBA-NEXT:  .LBB33_2: # %entry
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -1630,10 +1778,10 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-NEXT:    sgtz a2, a1
 ; RV32-NEXT:    sub a3, a0, a1
 ; RV32-NEXT:    slt a3, a3, a0
-; RV32-NEXT:    bne a2, a3, .LBB31_2
+; RV32-NEXT:    bne a2, a3, .LBB34_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB31_2: # %entry
+; RV32-NEXT:  .LBB34_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i32:
@@ -1642,10 +1790,10 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
 ; RV64-NEXT:    sext.w a3, a0
 ; RV64-NEXT:    sub a4, a3, a2
 ; RV64-NEXT:    subw a2, a3, a2
-; RV64-NEXT:    bne a2, a4, .LBB31_2
+; RV64-NEXT:    bne a2, a4, .LBB34_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB31_2: # %entry
+; RV64-NEXT:  .LBB34_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.select.i32:
@@ -1653,10 +1801,10 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
 ; RV32ZBA-NEXT:    sgtz a2, a1
 ; RV32ZBA-NEXT:    sub a3, a0, a1
 ; RV32ZBA-NEXT:    slt a3, a3, a0
-; RV32ZBA-NEXT:    bne a2, a3, .LBB31_2
+; RV32ZBA-NEXT:    bne a2, a3, .LBB34_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB31_2: # %entry
+; RV32ZBA-NEXT:  .LBB34_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.select.i32:
@@ -1665,10 +1813,10 @@ define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA-NEXT:    sext.w a3, a0
 ; RV64ZBA-NEXT:    sub a4, a3, a2
 ; RV64ZBA-NEXT:    subw a2, a3, a2
-; RV64ZBA-NEXT:    bne a2, a4, .LBB31_2
+; RV64ZBA-NEXT:    bne a2, a4, .LBB34_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB31_2: # %entry
+; RV64ZBA-NEXT:  .LBB34_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1731,11 +1879,11 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    xor a4, a1, a4
 ; RV32-NEXT:    xor a5, a1, a3
 ; RV32-NEXT:    and a4, a5, a4
-; RV32-NEXT:    bltz a4, .LBB33_2
+; RV32-NEXT:    bltz a4, .LBB36_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB33_2: # %entry
+; RV32-NEXT:  .LBB36_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i64:
@@ -1743,10 +1891,10 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
 ; RV64-NEXT:    sgtz a2, a1
 ; RV64-NEXT:    sub a3, a0, a1
 ; RV64-NEXT:    slt a3, a3, a0
-; RV64-NEXT:    bne a2, a3, .LBB33_2
+; RV64-NEXT:    bne a2, a3, .LBB36_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB33_2: # %entry
+; RV64-NEXT:  .LBB36_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.select.i64:
@@ -1757,11 +1905,11 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    xor a4, a1, a4
 ; RV32ZBA-NEXT:    xor a5, a1, a3
 ; RV32ZBA-NEXT:    and a4, a5, a4
-; RV32ZBA-NEXT:    bltz a4, .LBB33_2
+; RV32ZBA-NEXT:    bltz a4, .LBB36_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB33_2: # %entry
+; RV32ZBA-NEXT:  .LBB36_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.select.i64:
@@ -1769,10 +1917,10 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
 ; RV64ZBA-NEXT:    sgtz a2, a1
 ; RV64ZBA-NEXT:    sub a3, a0, a1
 ; RV64ZBA-NEXT:    slt a3, a3, a0
-; RV64ZBA-NEXT:    bne a2, a3, .LBB33_2
+; RV64ZBA-NEXT:    bne a2, a3, .LBB36_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB33_2: # %entry
+; RV64ZBA-NEXT:  .LBB36_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
@@ -1834,39 +1982,39 @@ define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: usubo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sub a2, a0, a1
-; RV32-NEXT:    bltu a0, a2, .LBB35_2
+; RV32-NEXT:    bltu a0, a2, .LBB38_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB35_2: # %entry
+; RV32-NEXT:  .LBB38_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    subw a2, a0, a1
 ; RV64-NEXT:    sext.w a3, a0
-; RV64-NEXT:    bltu a3, a2, .LBB35_2
+; RV64-NEXT:    bltu a3, a2, .LBB38_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB35_2: # %entry
+; RV64-NEXT:  .LBB38_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sub a2, a0, a1
-; RV32ZBA-NEXT:    bltu a0, a2, .LBB35_2
+; RV32ZBA-NEXT:    bltu a0, a2, .LBB38_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB35_2: # %entry
+; RV32ZBA-NEXT:  .LBB38_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    subw a2, a0, a1
 ; RV64ZBA-NEXT:    sext.w a3, a0
-; RV64ZBA-NEXT:    bltu a3, a2, .LBB35_2
+; RV64ZBA-NEXT:    bltu a3, a2, .LBB38_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB35_2: # %entry
+; RV64ZBA-NEXT:  .LBB38_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1918,28 +2066,28 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    sltu a4, a0, a2
 ; RV32-NEXT:    sub a5, a1, a3
 ; RV32-NEXT:    sub a4, a5, a4
-; RV32-NEXT:    beq a4, a1, .LBB37_2
+; RV32-NEXT:    beq a4, a1, .LBB40_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a4, a1, a4
-; RV32-NEXT:    beqz a4, .LBB37_3
-; RV32-NEXT:    j .LBB37_4
-; RV32-NEXT:  .LBB37_2:
+; RV32-NEXT:    beqz a4, .LBB40_3
+; RV32-NEXT:    j .LBB40_4
+; RV32-NEXT:  .LBB40_2:
 ; RV32-NEXT:    sub a4, a0, a2
 ; RV32-NEXT:    sltu a4, a0, a4
-; RV32-NEXT:    bnez a4, .LBB37_4
-; RV32-NEXT:  .LBB37_3: # %entry
+; RV32-NEXT:    bnez a4, .LBB40_4
+; RV32-NEXT:  .LBB40_3: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB37_4: # %entry
+; RV32-NEXT:  .LBB40_4: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a2, a0, a1
-; RV64-NEXT:    bltu a0, a2, .LBB37_2
+; RV64-NEXT:    bltu a0, a2, .LBB40_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB37_2: # %entry
+; RV64-NEXT:  .LBB40_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.select.i64:
@@ -1947,28 +2095,28 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
 ; RV32ZBA-NEXT:    sub a5, a1, a3
 ; RV32ZBA-NEXT:    sub a4, a5, a4
-; RV32ZBA-NEXT:    beq a4, a1, .LBB37_2
+; RV32ZBA-NEXT:    beq a4, a1, .LBB40_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a1, a4
-; RV32ZBA-NEXT:    beqz a4, .LBB37_3
-; RV32ZBA-NEXT:    j .LBB37_4
-; RV32ZBA-NEXT:  .LBB37_2:
+; RV32ZBA-NEXT:    beqz a4, .LBB40_3
+; RV32ZBA-NEXT:    j .LBB40_4
+; RV32ZBA-NEXT:  .LBB40_2:
 ; RV32ZBA-NEXT:    sub a4, a0, a2
 ; RV32ZBA-NEXT:    sltu a4, a0, a4
-; RV32ZBA-NEXT:    bnez a4, .LBB37_4
-; RV32ZBA-NEXT:  .LBB37_3: # %entry
+; RV32ZBA-NEXT:    bnez a4, .LBB40_4
+; RV32ZBA-NEXT:  .LBB40_3: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB37_4: # %entry
+; RV32ZBA-NEXT:  .LBB40_4: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sub a2, a0, a1
-; RV64ZBA-NEXT:    bltu a0, a2, .LBB37_2
+; RV64ZBA-NEXT:    bltu a0, a2, .LBB40_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB37_2: # %entry
+; RV64ZBA-NEXT:  .LBB40_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
@@ -1983,12 +2131,12 @@ define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    sltu a4, a0, a2
 ; RV32-NEXT:    sub a3, a1, a3
 ; RV32-NEXT:    sub a3, a3, a4
-; RV32-NEXT:    beq a3, a1, .LBB38_2
+; RV32-NEXT:    beq a3, a1, .LBB41_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB38_2:
+; RV32-NEXT:  .LBB41_2:
 ; RV32-NEXT:    sub a1, a0, a2
 ; RV32-NEXT:    sltu a0, a0, a1
 ; RV32-NEXT:    xori a0, a0, 1
@@ -2006,12 +2154,12 @@ define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
 ; RV32ZBA-NEXT:    sub a3, a1, a3
 ; RV32ZBA-NEXT:    sub a3, a3, a4
-; RV32ZBA-NEXT:    beq a3, a1, .LBB38_2
+; RV32ZBA-NEXT:    beq a3, a1, .LBB41_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB38_2:
+; RV32ZBA-NEXT:  .LBB41_2:
 ; RV32ZBA-NEXT:    sub a1, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a0, a1
 ; RV32ZBA-NEXT:    xori a0, a0, 1
@@ -2036,10 +2184,10 @@ define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-NEXT:    mulh a2, a0, a1
 ; RV32-NEXT:    mul a3, a0, a1
 ; RV32-NEXT:    srai a3, a3, 31
-; RV32-NEXT:    bne a2, a3, .LBB39_2
+; RV32-NEXT:    bne a2, a3, .LBB42_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB39_2: # %entry
+; RV32-NEXT:  .LBB42_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.select.i32:
@@ -2048,10 +2196,10 @@ define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
 ; RV64-NEXT:    sext.w a3, a0
 ; RV64-NEXT:    mul a4, a3, a2
 ; RV64-NEXT:    mulw a2, a3, a2
-; RV64-NEXT:    bne a2, a4, .LBB39_2
+; RV64-NEXT:    bne a2, a4, .LBB42_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB39_2: # %entry
+; RV64-NEXT:  .LBB42_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.select.i32:
@@ -2059,10 +2207,10 @@ define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
 ; RV32ZBA-NEXT:    mulh a2, a0, a1
 ; RV32ZBA-NEXT:    mul a3, a0, a1
 ; RV32ZBA-NEXT:    srai a3, a3, 31
-; RV32ZBA-NEXT:    bne a2, a3, .LBB39_2
+; RV32ZBA-NEXT:    bne a2, a3, .LBB42_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB39_2: # %entry
+; RV32ZBA-NEXT:  .LBB42_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.select.i32:
@@ -2071,10 +2219,10 @@ define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA-NEXT:    sext.w a3, a0
 ; RV64ZBA-NEXT:    mul a4, a3, a2
 ; RV64ZBA-NEXT:    mulw a2, a3, a2
-; RV64ZBA-NEXT:    bne a2, a4, .LBB39_2
+; RV64ZBA-NEXT:    bne a2, a4, .LBB42_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB39_2: # %entry
+; RV64ZBA-NEXT:  .LBB42_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -2151,11 +2299,11 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    addi a4, sp, 8
 ; RV32-NEXT:    call __mulodi4@plt
 ; RV32-NEXT:    lw a0, 8(sp)
-; RV32-NEXT:    bnez a0, .LBB41_2
+; RV32-NEXT:    bnez a0, .LBB44_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv s1, s3
 ; RV32-NEXT:    mv s0, s2
-; RV32-NEXT:  .LBB41_2: # %entry
+; RV32-NEXT:  .LBB44_2: # %entry
 ; RV32-NEXT:    mv a0, s1
 ; RV32-NEXT:    mv a1, s0
 ; RV32-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
@@ -2171,10 +2319,10 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
 ; RV64-NEXT:    mulh a2, a0, a1
 ; RV64-NEXT:    mul a3, a0, a1
 ; RV64-NEXT:    srai a3, a3, 63
-; RV64-NEXT:    bne a2, a3, .LBB41_2
+; RV64-NEXT:    bne a2, a3, .LBB44_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB41_2: # %entry
+; RV64-NEXT:  .LBB44_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.select.i64:
@@ -2199,11 +2347,11 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    addi a4, sp, 8
 ; RV32ZBA-NEXT:    call __mulodi4@plt
 ; RV32ZBA-NEXT:    lw a0, 8(sp)
-; RV32ZBA-NEXT:    bnez a0, .LBB41_2
+; RV32ZBA-NEXT:    bnez a0, .LBB44_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv s1, s3
 ; RV32ZBA-NEXT:    mv s0, s2
-; RV32ZBA-NEXT:  .LBB41_2: # %entry
+; RV32ZBA-NEXT:  .LBB44_2: # %entry
 ; RV32ZBA-NEXT:    mv a0, s1
 ; RV32ZBA-NEXT:    mv a1, s0
 ; RV32ZBA-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
@@ -2219,10 +2367,10 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
 ; RV64ZBA-NEXT:    mulh a2, a0, a1
 ; RV64ZBA-NEXT:    mul a3, a0, a1
 ; RV64ZBA-NEXT:    srai a3, a3, 63
-; RV64ZBA-NEXT:    bne a2, a3, .LBB41_2
+; RV64ZBA-NEXT:    bne a2, a3, .LBB44_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB41_2: # %entry
+; RV64ZBA-NEXT:  .LBB44_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
@@ -2290,10 +2438,10 @@ define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: umulo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mulhu a2, a0, a1
-; RV32-NEXT:    bnez a2, .LBB43_2
+; RV32-NEXT:    bnez a2, .LBB46_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB43_2: # %entry
+; RV32-NEXT:  .LBB46_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.select.i32:
@@ -2302,19 +2450,19 @@ define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
 ; RV64-NEXT:    slli a3, a0, 32
 ; RV64-NEXT:    mulhu a2, a3, a2
 ; RV64-NEXT:    srli a2, a2, 32
-; RV64-NEXT:    bnez a2, .LBB43_2
+; RV64-NEXT:    bnez a2, .LBB46_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB43_2: # %entry
+; RV64-NEXT:  .LBB46_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulhu a2, a0, a1
-; RV32ZBA-NEXT:    bnez a2, .LBB43_2
+; RV32ZBA-NEXT:    bnez a2, .LBB46_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB43_2: # %entry
+; RV32ZBA-NEXT:  .LBB46_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.select.i32:
@@ -2323,10 +2471,10 @@ define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA-NEXT:    zext.w a3, a0
 ; RV64ZBA-NEXT:    mul a2, a3, a2
 ; RV64ZBA-NEXT:    srli a2, a2, 32
-; RV64ZBA-NEXT:    bnez a2, .LBB43_2
+; RV64ZBA-NEXT:    bnez a2, .LBB46_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB43_2: # %entry
+; RV64ZBA-NEXT:  .LBB46_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -2391,20 +2539,20 @@ define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    snez a5, a5
 ; RV32-NEXT:    or a4, a4, a5
 ; RV32-NEXT:    or a4, a4, a6
-; RV32-NEXT:    bnez a4, .LBB45_2
+; RV32-NEXT:    bnez a4, .LBB48_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB45_2: # %entry
+; RV32-NEXT:  .LBB48_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a2, a0, a1
-; RV64-NEXT:    bnez a2, .LBB45_2
+; RV64-NEXT:    bnez a2, .LBB48_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB45_2: # %entry
+; RV64-NEXT:  .LBB48_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.select.i64:
@@ -2425,20 +2573,20 @@ define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    snez a5, a5
 ; RV32ZBA-NEXT:    or a4, a4, a5
 ; RV32ZBA-NEXT:    or a4, a4, a6
-; RV32ZBA-NEXT:    bnez a4, .LBB45_2
+; RV32ZBA-NEXT:    bnez a4, .LBB48_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB45_2: # %entry
+; RV32ZBA-NEXT:  .LBB48_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    mulhu a2, a0, a1
-; RV64ZBA-NEXT:    bnez a2, .LBB45_2
+; RV64ZBA-NEXT:    bnez a2, .LBB48_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB45_2: # %entry
+; RV64ZBA-NEXT:  .LBB48_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
@@ -2518,11 +2666,11 @@ define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    slt a0, a2, a0
 ; RV32-NEXT:    slti a1, a1, 0
-; RV32-NEXT:    beq a1, a0, .LBB47_2
+; RV32-NEXT:    beq a1, a0, .LBB50_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB47_2: # %continue
+; RV32-NEXT:  .LBB50_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
@@ -2532,11 +2680,11 @@ define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    addw a0, a0, a1
-; RV64-NEXT:    beq a0, a2, .LBB47_2
+; RV64-NEXT:    beq a0, a2, .LBB50_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB47_2: # %continue
+; RV64-NEXT:  .LBB50_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -2545,11 +2693,11 @@ define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
 ; RV32ZBA-NEXT:    add a2, a0, a1
 ; RV32ZBA-NEXT:    slt a0, a2, a0
 ; RV32ZBA-NEXT:    slti a1, a1, 0
-; RV32ZBA-NEXT:    beq a1, a0, .LBB47_2
+; RV32ZBA-NEXT:    beq a1, a0, .LBB50_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB47_2: # %continue
+; RV32ZBA-NEXT:  .LBB50_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -2559,11 +2707,11 @@ define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    add a2, a0, a1
 ; RV64ZBA-NEXT:    addw a0, a0, a1
-; RV64ZBA-NEXT:    beq a0, a2, .LBB47_2
+; RV64ZBA-NEXT:    beq a0, a2, .LBB50_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB47_2: # %continue
+; RV64ZBA-NEXT:  .LBB50_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -2590,11 +2738,11 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    bgez a0, .LBB48_2
+; RV32-NEXT:    bgez a0, .LBB51_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB48_2: # %continue
+; RV32-NEXT:  .LBB51_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
@@ -2603,11 +2751,11 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    slt a0, a2, a0
 ; RV64-NEXT:    slti a1, a1, 0
-; RV64-NEXT:    beq a1, a0, .LBB48_2
+; RV64-NEXT:    beq a1, a0, .LBB51_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB48_2: # %continue
+; RV64-NEXT:  .LBB51_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -2621,11 +2769,11 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    not a1, a1
 ; RV32ZBA-NEXT:    and a0, a1, a0
-; RV32ZBA-NEXT:    bgez a0, .LBB48_2
+; RV32ZBA-NEXT:    bgez a0, .LBB51_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB48_2: # %continue
+; RV32ZBA-NEXT:  .LBB51_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -2634,11 +2782,11 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
 ; RV64ZBA-NEXT:    add a2, a0, a1
 ; RV64ZBA-NEXT:    slt a0, a2, a0
 ; RV64ZBA-NEXT:    slti a1, a1, 0
-; RV64ZBA-NEXT:    beq a1, a0, .LBB48_2
+; RV64ZBA-NEXT:    beq a1, a0, .LBB51_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB48_2: # %continue
+; RV64ZBA-NEXT:  .LBB51_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -2658,11 +2806,11 @@ define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: uaddo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a1, a0, a1
-; RV32-NEXT:    bgeu a1, a0, .LBB49_2
+; RV32-NEXT:    bgeu a1, a0, .LBB52_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB49_2: # %continue
+; RV32-NEXT:  .LBB52_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
@@ -2670,22 +2818,22 @@ define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addw a1, a0, a1
 ; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    bgeu a1, a0, .LBB49_2
+; RV64-NEXT:    bgeu a1, a0, .LBB52_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB49_2: # %continue
+; RV64-NEXT:  .LBB52_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a1, a0, a1
-; RV32ZBA-NEXT:    bgeu a1, a0, .LBB49_2
+; RV32ZBA-NEXT:    bgeu a1, a0, .LBB52_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB49_2: # %continue
+; RV32ZBA-NEXT:  .LBB52_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -2693,11 +2841,11 @@ define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    addw a1, a0, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
-; RV64ZBA-NEXT:    bgeu a1, a0, .LBB49_2
+; RV64ZBA-NEXT:    bgeu a1, a0, .LBB52_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB49_2: # %continue
+; RV64ZBA-NEXT:  .LBB52_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -2720,26 +2868,26 @@ define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a2, a3, a0
-; RV32-NEXT:    beq a2, a1, .LBB50_2
+; RV32-NEXT:    beq a2, a1, .LBB53_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
-; RV32-NEXT:  .LBB50_2: # %entry
-; RV32-NEXT:    beqz a0, .LBB50_4
+; RV32-NEXT:  .LBB53_2: # %entry
+; RV32-NEXT:    beqz a0, .LBB53_4
 ; RV32-NEXT:  # %bb.3: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB50_4: # %continue
+; RV32-NEXT:  .LBB53_4: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a1, a0, a1
-; RV64-NEXT:    bgeu a1, a0, .LBB50_2
+; RV64-NEXT:    bgeu a1, a0, .LBB53_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB50_2: # %continue
+; RV64-NEXT:  .LBB53_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -2749,26 +2897,26 @@ define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a2, a3, a0
-; RV32ZBA-NEXT:    beq a2, a1, .LBB50_2
+; RV32ZBA-NEXT:    beq a2, a1, .LBB53_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
-; RV32ZBA-NEXT:  .LBB50_2: # %entry
-; RV32ZBA-NEXT:    beqz a0, .LBB50_4
+; RV32ZBA-NEXT:  .LBB53_2: # %entry
+; RV32ZBA-NEXT:    beqz a0, .LBB53_4
 ; RV32ZBA-NEXT:  # %bb.3: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB50_4: # %continue
+; RV32ZBA-NEXT:  .LBB53_4: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a1, a0, a1
-; RV64ZBA-NEXT:    bgeu a1, a0, .LBB50_2
+; RV64ZBA-NEXT:    bgeu a1, a0, .LBB53_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB50_2: # %continue
+; RV64ZBA-NEXT:  .LBB53_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -2790,11 +2938,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-NEXT:    sgtz a2, a1
 ; RV32-NEXT:    sub a1, a0, a1
 ; RV32-NEXT:    slt a0, a1, a0
-; RV32-NEXT:    beq a2, a0, .LBB51_2
+; RV32-NEXT:    beq a2, a0, .LBB54_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB51_2: # %continue
+; RV32-NEXT:  .LBB54_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
@@ -2804,11 +2952,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    sub a2, a0, a1
 ; RV64-NEXT:    subw a0, a0, a1
-; RV64-NEXT:    beq a0, a2, .LBB51_2
+; RV64-NEXT:    beq a0, a2, .LBB54_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB51_2: # %continue
+; RV64-NEXT:  .LBB54_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -2817,11 +2965,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
 ; RV32ZBA-NEXT:    sgtz a2, a1
 ; RV32ZBA-NEXT:    sub a1, a0, a1
 ; RV32ZBA-NEXT:    slt a0, a1, a0
-; RV32ZBA-NEXT:    beq a2, a0, .LBB51_2
+; RV32ZBA-NEXT:    beq a2, a0, .LBB54_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB51_2: # %continue
+; RV32ZBA-NEXT:  .LBB54_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -2831,11 +2979,11 @@ define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    sub a2, a0, a1
 ; RV64ZBA-NEXT:    subw a0, a0, a1
-; RV64ZBA-NEXT:    beq a0, a2, .LBB51_2
+; RV64ZBA-NEXT:    beq a0, a2, .LBB54_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB51_2: # %continue
+; RV64ZBA-NEXT:  .LBB54_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -2860,11 +3008,11 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    bgez a0, .LBB52_2
+; RV32-NEXT:    bgez a0, .LBB55_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB52_2: # %continue
+; RV32-NEXT:  .LBB55_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
@@ -2873,11 +3021,11 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
 ; RV64-NEXT:    sgtz a2, a1
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    slt a0, a1, a0
-; RV64-NEXT:    beq a2, a0, .LBB52_2
+; RV64-NEXT:    beq a2, a0, .LBB55_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB52_2: # %continue
+; RV64-NEXT:  .LBB55_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -2889,11 +3037,11 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    and a0, a1, a0
-; RV32ZBA-NEXT:    bgez a0, .LBB52_2
+; RV32ZBA-NEXT:    bgez a0, .LBB55_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB52_2: # %continue
+; RV32ZBA-NEXT:  .LBB55_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -2902,11 +3050,11 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
 ; RV64ZBA-NEXT:    sgtz a2, a1
 ; RV64ZBA-NEXT:    sub a1, a0, a1
 ; RV64ZBA-NEXT:    slt a0, a1, a0
-; RV64ZBA-NEXT:    beq a2, a0, .LBB52_2
+; RV64ZBA-NEXT:    beq a2, a0, .LBB55_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB52_2: # %continue
+; RV64ZBA-NEXT:  .LBB55_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -2926,11 +3074,11 @@ define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: usubo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sub a1, a0, a1
-; RV32-NEXT:    bgeu a0, a1, .LBB53_2
+; RV32-NEXT:    bgeu a0, a1, .LBB56_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB53_2: # %continue
+; RV32-NEXT:  .LBB56_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
@@ -2938,22 +3086,22 @@ define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    subw a1, a0, a1
 ; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    bgeu a0, a1, .LBB53_2
+; RV64-NEXT:    bgeu a0, a1, .LBB56_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB53_2: # %continue
+; RV64-NEXT:  .LBB56_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sub a1, a0, a1
-; RV32ZBA-NEXT:    bgeu a0, a1, .LBB53_2
+; RV32ZBA-NEXT:    bgeu a0, a1, .LBB56_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB53_2: # %continue
+; RV32ZBA-NEXT:  .LBB56_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -2961,11 +3109,11 @@ define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    subw a1, a0, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
-; RV64ZBA-NEXT:    bgeu a0, a1, .LBB53_2
+; RV64ZBA-NEXT:    bgeu a0, a1, .LBB56_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB53_2: # %continue
+; RV64ZBA-NEXT:  .LBB56_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -2987,29 +3135,29 @@ define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    sltu a4, a0, a2
 ; RV32-NEXT:    sub a3, a1, a3
 ; RV32-NEXT:    sub a3, a3, a4
-; RV32-NEXT:    beq a3, a1, .LBB54_3
+; RV32-NEXT:    beq a3, a1, .LBB57_3
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
-; RV32-NEXT:    bnez a0, .LBB54_4
-; RV32-NEXT:  .LBB54_2: # %continue
+; RV32-NEXT:    bnez a0, .LBB57_4
+; RV32-NEXT:  .LBB57_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB54_3:
+; RV32-NEXT:  .LBB57_3:
 ; RV32-NEXT:    sub a1, a0, a2
 ; RV32-NEXT:    sltu a0, a0, a1
-; RV32-NEXT:    beqz a0, .LBB54_2
-; RV32-NEXT:  .LBB54_4: # %overflow
+; RV32-NEXT:    beqz a0, .LBB57_2
+; RV32-NEXT:  .LBB57_4: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a1, a0, a1
-; RV64-NEXT:    bgeu a0, a1, .LBB54_2
+; RV64-NEXT:    bgeu a0, a1, .LBB57_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB54_2: # %continue
+; RV64-NEXT:  .LBB57_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -3018,29 +3166,29 @@ define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
 ; RV32ZBA-NEXT:    sub a3, a1, a3
 ; RV32ZBA-NEXT:    sub a3, a3, a4
-; RV32ZBA-NEXT:    beq a3, a1, .LBB54_3
+; RV32ZBA-NEXT:    beq a3, a1, .LBB57_3
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
-; RV32ZBA-NEXT:    bnez a0, .LBB54_4
-; RV32ZBA-NEXT:  .LBB54_2: # %continue
+; RV32ZBA-NEXT:    bnez a0, .LBB57_4
+; RV32ZBA-NEXT:  .LBB57_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB54_3:
+; RV32ZBA-NEXT:  .LBB57_3:
 ; RV32ZBA-NEXT:    sub a1, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a0, a1
-; RV32ZBA-NEXT:    beqz a0, .LBB54_2
-; RV32ZBA-NEXT:  .LBB54_4: # %overflow
+; RV32ZBA-NEXT:    beqz a0, .LBB57_2
+; RV32ZBA-NEXT:  .LBB57_4: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sub a1, a0, a1
-; RV64ZBA-NEXT:    bgeu a0, a1, .LBB54_2
+; RV64ZBA-NEXT:    bgeu a0, a1, .LBB57_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB54_2: # %continue
+; RV64ZBA-NEXT:  .LBB57_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -3062,11 +3210,11 @@ define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-NEXT:    mulh a2, a0, a1
 ; RV32-NEXT:    mul a0, a0, a1
 ; RV32-NEXT:    srai a0, a0, 31
-; RV32-NEXT:    beq a2, a0, .LBB55_2
+; RV32-NEXT:    beq a2, a0, .LBB58_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB55_2: # %continue
+; RV32-NEXT:  .LBB58_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
@@ -3076,11 +3224,11 @@ define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    mul a2, a0, a1
 ; RV64-NEXT:    mulw a0, a0, a1
-; RV64-NEXT:    beq a0, a2, .LBB55_2
+; RV64-NEXT:    beq a0, a2, .LBB58_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB55_2: # %continue
+; RV64-NEXT:  .LBB58_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -3089,11 +3237,11 @@ define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
 ; RV32ZBA-NEXT:    mulh a2, a0, a1
 ; RV32ZBA-NEXT:    mul a0, a0, a1
 ; RV32ZBA-NEXT:    srai a0, a0, 31
-; RV32ZBA-NEXT:    beq a2, a0, .LBB55_2
+; RV32ZBA-NEXT:    beq a2, a0, .LBB58_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB55_2: # %continue
+; RV32ZBA-NEXT:  .LBB58_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -3103,11 +3251,11 @@ define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    mul a2, a0, a1
 ; RV64ZBA-NEXT:    mulw a0, a0, a1
-; RV64ZBA-NEXT:    beq a0, a2, .LBB55_2
+; RV64ZBA-NEXT:    beq a0, a2, .LBB58_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB55_2: # %continue
+; RV64ZBA-NEXT:  .LBB58_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -3134,13 +3282,13 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    addi a4, sp, 8
 ; RV32-NEXT:    call __mulodi4@plt
 ; RV32-NEXT:    lw a0, 8(sp)
-; RV32-NEXT:    beqz a0, .LBB56_2
+; RV32-NEXT:    beqz a0, .LBB59_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
-; RV32-NEXT:    j .LBB56_3
-; RV32-NEXT:  .LBB56_2: # %continue
+; RV32-NEXT:    j .LBB59_3
+; RV32-NEXT:  .LBB59_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
-; RV32-NEXT:  .LBB56_3: # %overflow
+; RV32-NEXT:  .LBB59_3: # %overflow
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
@@ -3150,11 +3298,11 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
 ; RV64-NEXT:    mulh a2, a0, a1
 ; RV64-NEXT:    mul a0, a0, a1
 ; RV64-NEXT:    srai a0, a0, 63
-; RV64-NEXT:    beq a2, a0, .LBB56_2
+; RV64-NEXT:    beq a2, a0, .LBB59_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB56_2: # %continue
+; RV64-NEXT:  .LBB59_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -3168,13 +3316,13 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    addi a4, sp, 8
 ; RV32ZBA-NEXT:    call __mulodi4@plt
 ; RV32ZBA-NEXT:    lw a0, 8(sp)
-; RV32ZBA-NEXT:    beqz a0, .LBB56_2
+; RV32ZBA-NEXT:    beqz a0, .LBB59_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
-; RV32ZBA-NEXT:    j .LBB56_3
-; RV32ZBA-NEXT:  .LBB56_2: # %continue
+; RV32ZBA-NEXT:    j .LBB59_3
+; RV32ZBA-NEXT:  .LBB59_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
-; RV32ZBA-NEXT:  .LBB56_3: # %overflow
+; RV32ZBA-NEXT:  .LBB59_3: # %overflow
 ; RV32ZBA-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32ZBA-NEXT:    addi sp, sp, 16
 ; RV32ZBA-NEXT:    ret
@@ -3184,11 +3332,11 @@ define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
 ; RV64ZBA-NEXT:    mulh a2, a0, a1
 ; RV64ZBA-NEXT:    mul a0, a0, a1
 ; RV64ZBA-NEXT:    srai a0, a0, 63
-; RV64ZBA-NEXT:    beq a2, a0, .LBB56_2
+; RV64ZBA-NEXT:    beq a2, a0, .LBB59_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB56_2: # %continue
+; RV64ZBA-NEXT:  .LBB59_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -3217,13 +3365,13 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
 ; RV32-NEXT:    addi a4, sp, 8
 ; RV32-NEXT:    call __mulodi4@plt
 ; RV32-NEXT:    lw a0, 8(sp)
-; RV32-NEXT:    beqz a0, .LBB57_2
+; RV32-NEXT:    beqz a0, .LBB60_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
-; RV32-NEXT:    j .LBB57_3
-; RV32-NEXT:  .LBB57_2: # %continue
+; RV32-NEXT:    j .LBB60_3
+; RV32-NEXT:  .LBB60_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
-; RV32-NEXT:  .LBB57_3: # %overflow
+; RV32-NEXT:  .LBB60_3: # %overflow
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
@@ -3234,11 +3382,11 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
 ; RV64-NEXT:    mulh a2, a0, a1
 ; RV64-NEXT:    mul a0, a0, a1
 ; RV64-NEXT:    srai a0, a0, 63
-; RV64-NEXT:    beq a2, a0, .LBB57_2
+; RV64-NEXT:    beq a2, a0, .LBB60_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB57_2: # %continue
+; RV64-NEXT:  .LBB60_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -3254,13 +3402,13 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
 ; RV32ZBA-NEXT:    addi a4, sp, 8
 ; RV32ZBA-NEXT:    call __mulodi4@plt
 ; RV32ZBA-NEXT:    lw a0, 8(sp)
-; RV32ZBA-NEXT:    beqz a0, .LBB57_2
+; RV32ZBA-NEXT:    beqz a0, .LBB60_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
-; RV32ZBA-NEXT:    j .LBB57_3
-; RV32ZBA-NEXT:  .LBB57_2: # %continue
+; RV32ZBA-NEXT:    j .LBB60_3
+; RV32ZBA-NEXT:  .LBB60_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
-; RV32ZBA-NEXT:  .LBB57_3: # %overflow
+; RV32ZBA-NEXT:  .LBB60_3: # %overflow
 ; RV32ZBA-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32ZBA-NEXT:    addi sp, sp, 16
 ; RV32ZBA-NEXT:    ret
@@ -3271,11 +3419,11 @@ define zeroext i1 @smulo2.br.i64(i64 %v1) {
 ; RV64ZBA-NEXT:    mulh a2, a0, a1
 ; RV64ZBA-NEXT:    mul a0, a0, a1
 ; RV64ZBA-NEXT:    srai a0, a0, 63
-; RV64ZBA-NEXT:    beq a2, a0, .LBB57_2
+; RV64ZBA-NEXT:    beq a2, a0, .LBB60_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB57_2: # %continue
+; RV64ZBA-NEXT:  .LBB60_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -3295,11 +3443,11 @@ define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: umulo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mulhu a0, a0, a1
-; RV32-NEXT:    beqz a0, .LBB58_2
+; RV32-NEXT:    beqz a0, .LBB61_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB58_2: # %continue
+; RV32-NEXT:  .LBB61_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
@@ -3309,22 +3457,22 @@ define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    mulhu a0, a0, a1
 ; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    beqz a0, .LBB58_2
+; RV64-NEXT:    beqz a0, .LBB61_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB58_2: # %continue
+; RV64-NEXT:  .LBB61_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulhu a0, a0, a1
-; RV32ZBA-NEXT:    beqz a0, .LBB58_2
+; RV32ZBA-NEXT:    beqz a0, .LBB61_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB58_2: # %continue
+; RV32ZBA-NEXT:  .LBB61_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
@@ -3334,11 +3482,11 @@ define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
 ; RV64ZBA-NEXT:    zext.w a0, a0
 ; RV64ZBA-NEXT:    mul a0, a0, a1
 ; RV64ZBA-NEXT:    srli a0, a0, 32
-; RV64ZBA-NEXT:    beqz a0, .LBB58_2
+; RV64ZBA-NEXT:    beqz a0, .LBB61_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB58_2: # %continue
+; RV64ZBA-NEXT:  .LBB61_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -3373,22 +3521,22 @@ define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    or a0, a0, a6
-; RV32-NEXT:    beqz a0, .LBB59_2
+; RV32-NEXT:    beqz a0, .LBB62_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB59_2: # %continue
+; RV32-NEXT:  .LBB62_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a0, a0, a1
-; RV64-NEXT:    beqz a0, .LBB59_2
+; RV64-NEXT:    beqz a0, .LBB62_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB59_2: # %continue
+; RV64-NEXT:  .LBB62_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -3410,22 +3558,22 @@ define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
 ; RV32ZBA-NEXT:    snez a0, a0
 ; RV32ZBA-NEXT:    or a0, a1, a0
 ; RV32ZBA-NEXT:    or a0, a0, a6
-; RV32ZBA-NEXT:    beqz a0, .LBB59_2
+; RV32ZBA-NEXT:    beqz a0, .LBB62_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB59_2: # %continue
+; RV32ZBA-NEXT:  .LBB62_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    mulhu a0, a0, a1
-; RV64ZBA-NEXT:    beqz a0, .LBB59_2
+; RV64ZBA-NEXT:    beqz a0, .LBB62_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB59_2: # %continue
+; RV64ZBA-NEXT:  .LBB62_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
@@ -3448,26 +3596,26 @@ define zeroext i1 @umulo2.br.i64(i64 %v1) {
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a2, a1, a1
 ; RV32-NEXT:    add a2, a2, a0
-; RV32-NEXT:    beq a2, a1, .LBB60_2
+; RV32-NEXT:    beq a2, a1, .LBB63_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
-; RV32-NEXT:  .LBB60_2: # %entry
-; RV32-NEXT:    beqz a0, .LBB60_4
+; RV32-NEXT:  .LBB63_2: # %entry
+; RV32-NEXT:    beqz a0, .LBB63_4
 ; RV32-NEXT:  # %bb.3: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB60_4: # %continue
+; RV32-NEXT:  .LBB63_4: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo2.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a1, a0, a0
-; RV64-NEXT:    bgeu a1, a0, .LBB60_2
+; RV64-NEXT:    bgeu a1, a0, .LBB63_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB60_2: # %continue
+; RV64-NEXT:  .LBB63_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
@@ -3477,26 +3625,26 @@ define zeroext i1 @umulo2.br.i64(i64 %v1) {
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a2, a1, a1
 ; RV32ZBA-NEXT:    add a2, a2, a0
-; RV32ZBA-NEXT:    beq a2, a1, .LBB60_2
+; RV32ZBA-NEXT:    beq a2, a1, .LBB63_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
-; RV32ZBA-NEXT:  .LBB60_2: # %entry
-; RV32ZBA-NEXT:    beqz a0, .LBB60_4
+; RV32ZBA-NEXT:  .LBB63_2: # %entry
+; RV32ZBA-NEXT:    beqz a0, .LBB63_4
 ; RV32ZBA-NEXT:  # %bb.3: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB60_4: # %continue
+; RV32ZBA-NEXT:  .LBB63_4: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo2.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a1, a0, a0
-; RV64ZBA-NEXT:    bgeu a1, a0, .LBB60_2
+; RV64ZBA-NEXT:    bgeu a1, a0, .LBB63_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB60_2: # %continue
+; RV64ZBA-NEXT:  .LBB63_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry: