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[SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCC
First half of PR40800, this patch adds DAG undef handling to icmp instructions to match the behaviour in llvm::ConstantFoldCompareInstruction and SimplifyICmpInst, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.). This involved a lot of tweaking to reduced tests as bugpoint loves to reduce icmp arguments to undef........ Differential Revision: https://reviews.llvm.org/D59363 llvm-svn: 356938
This commit is contained in:
Simon Pilgrim
parent
e9a8be11b4
commit
51fa2dddea
@ -1974,9 +1974,25 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
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break;
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}
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// We can always fold X == X for integer setcc's.
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if (N1 == N2 && OpVT.isInteger())
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return getBoolConstant(ISD::isTrueWhenEqual(Cond), dl, VT, OpVT);
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if (OpVT.isInteger()) {
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// For EQ and NE, we can always pick a value for the undef to make the
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// predicate pass or fail, so we can return undef.
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// Matches behavior in llvm::ConstantFoldCompareInstruction.
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// icmp eq/ne X, undef -> undef.
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if ((N1.isUndef() || N2.isUndef()) &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE))
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return getUNDEF(VT);
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// If both operands are undef, we can return undef for int comparison.
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// icmp undef, undef -> undef.
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if (N1.isUndef() && N2.isUndef())
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return getUNDEF(VT);
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// icmp X, X -> true/false
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// icmp X, undef -> true/false because undef could be X.
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if (N1 == N2)
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return getBoolConstant(ISD::isTrueWhenEqual(Cond), dl, VT, OpVT);
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}
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if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2)) {
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const APInt &C2 = N2C->getAPIntValue();
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@ -172,9 +172,7 @@ define <4 x i32> @test_urem_both(<4 x i32> %X) nounwind readnone {
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define <4 x i32> @test_urem_div_undef(<4 x i32> %X) nounwind readnone {
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; CHECK-LABEL: test_urem_div_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 undef, i32 5>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
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@ -207,9 +205,7 @@ define <4 x i32> @test_urem_comp_undef(<4 x i32> %X) nounwind readnone {
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define <4 x i32> @test_urem_both_undef(<4 x i32> %X) nounwind readnone {
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; CHECK-LABEL: test_urem_both_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 undef, i32 5>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 undef, i32 0, i32 0>
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@ -4,7 +4,7 @@
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target datalayout = "E-m:e-i64:64-n32:64-S128"
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target triple = "sparc64-unknown-linux-gnu"
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define void @f() align 2 {
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define void @f(i64 %a0) align 2 {
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; CHECK-LABEL: f:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ! %bb.0: ! %entry
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@ -22,7 +22,7 @@ define void @f() align 2 {
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; CHECK-NEXT: .LBB0_1: ! %cond.false
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; CHECK-NEXT: .LBB0_4: ! %exit.i85
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entry:
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%cmp = icmp eq i64 undef, 0
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%cmp = icmp eq i64 %a0, 0
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br i1 %cmp, label %targetblock, label %cond.false
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cond.false:
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@ -10,11 +10,9 @@ define void @handle_vector_size_attribute() nounwind {
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; CHECK-NEXT: ja .LBB0_2
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; CHECK-NEXT: # %bb.1: # %bb77
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; CHECK-NEXT: movb 0, %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax def $ax
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; CHECK-NEXT: divb 0
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: cmpq %rax, %rax
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; CHECK-NEXT: movb 0, %al
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: .LBB0_2: # %bb84
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; CHECK-NEXT: retq
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entry:
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@ -1844,70 +1844,70 @@ define i96 @test_insertelement_variable_v96i1(<96 x i8> %a, i8 %b, i32 %index) {
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; KNL-NEXT: andq $-128, %rsp
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; KNL-NEXT: subq $256, %rsp ## imm = 0x100
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; KNL-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; KNL-NEXT: vpinsrb $1, 488(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $2, 496(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $3, 504(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $4, 512(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $5, 520(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $6, 528(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $7, 536(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $8, 544(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $9, 552(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $10, 560(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $11, 568(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $12, 576(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $13, 584(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $14, 592(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $15, 600(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $1, 232(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $2, 240(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $3, 248(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $4, 256(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $5, 264(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $6, 272(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $7, 280(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $8, 288(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $9, 296(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $10, 304(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $11, 312(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $12, 320(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $13, 328(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $14, 336(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vpinsrb $15, 344(%rbp), %xmm0, %xmm0
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; KNL-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; KNL-NEXT: vpinsrb $1, 616(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $2, 624(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $3, 632(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $4, 640(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $5, 648(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $6, 656(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $7, 664(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $8, 672(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $9, 680(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $10, 688(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $11, 696(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $12, 704(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $13, 712(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $14, 720(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $15, 728(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $1, 360(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $2, 368(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $3, 376(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $4, 384(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $5, 392(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $6, 400(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $7, 408(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $8, 416(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $9, 424(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $10, 432(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $11, 440(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $12, 448(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $13, 456(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $14, 464(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $15, 472(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; KNL-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; KNL-NEXT: vpinsrb $1, 232(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $2, 240(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $3, 248(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $4, 256(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $5, 264(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $6, 272(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $7, 280(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $8, 288(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $9, 296(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $10, 304(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $11, 312(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $12, 320(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $13, 328(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $14, 336(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $15, 344(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $1, 488(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $2, 496(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $3, 504(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $4, 512(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $5, 520(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $6, 528(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $7, 536(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $8, 544(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $9, 552(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $10, 560(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $11, 568(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $12, 576(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $13, 584(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $14, 592(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vpinsrb $15, 600(%rbp), %xmm1, %xmm1
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; KNL-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; KNL-NEXT: vpinsrb $1, 360(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $2, 368(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $3, 376(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $4, 384(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $5, 392(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $6, 400(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $7, 408(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $8, 416(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $9, 424(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $10, 432(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $11, 440(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $12, 448(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $13, 456(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $14, 464(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $15, 472(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $1, 616(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $2, 624(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $3, 632(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $4, 640(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $5, 648(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $6, 656(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $7, 664(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $8, 672(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $9, 680(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $10, 688(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $11, 696(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $12, 704(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $13, 712(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $14, 720(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vpinsrb $15, 728(%rbp), %xmm2, %xmm2
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; KNL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
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; KNL-NEXT: vmovd %edi, %xmm2
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; KNL-NEXT: vpinsrb $1, %esi, %xmm2, %xmm2
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@ -1952,7 +1952,6 @@ define i96 @test_insertelement_variable_v96i1(<96 x i8> %a, i8 %b, i32 %index) {
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; KNL-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
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; KNL-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0
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; KNL-NEXT: cmpb $0, 736(%rbp)
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; KNL-NEXT: vmovdqa %ymm3, {{[0-9]+}}(%rsp)
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; KNL-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)
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; KNL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
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; KNL-NEXT: vmovdqa %ymm2, (%rsp)
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@ -1252,106 +1252,6 @@ define void @clamp(i32 %src, i16* %dst) {
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ret void
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}
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define void @test19() {
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; This is a massive reduction of an llvm-stress test case that generates
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; interesting chains feeding setcc and eventually a f32 select operation. This
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; is intended to exercise the SELECT formation in the DAG combine simplifying
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; a simplified select_cc node. If it it regresses and is no longer triggering
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; that code path, it can be deleted.
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;
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; CHECK-LABEL: test19:
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; CHECK: ## %bb.0: ## %BB
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: movb $1, %cl
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB23_1: ## %CF
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: testb %cl, %cl
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; CHECK-NEXT: jne LBB23_1
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; CHECK-NEXT: ## %bb.2: ## %CF250
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; CHECK-NEXT: ## in Loop: Header=BB23_1 Depth=1
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; CHECK-NEXT: jne LBB23_1
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB23_3: ## %CF242
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpl %eax, %eax
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; CHECK-NEXT: ucomiss %xmm0, %xmm0
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; CHECK-NEXT: jp LBB23_3
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; CHECK-NEXT: ## %bb.4: ## %CF244
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; CHECK-NEXT: retq
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;
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; ATHLON-LABEL: test19:
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; ATHLON: ## %bb.0: ## %BB
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; ATHLON-NEXT: movb $1, %al
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; ATHLON-NEXT: .p2align 4, 0x90
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; ATHLON-NEXT: LBB23_1: ## %CF
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; ATHLON-NEXT: ## =>This Inner Loop Header: Depth=1
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; ATHLON-NEXT: testb %al, %al
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; ATHLON-NEXT: jne LBB23_1
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; ATHLON-NEXT: ## %bb.2: ## %CF250
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; ATHLON-NEXT: ## in Loop: Header=BB23_1 Depth=1
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; ATHLON-NEXT: jne LBB23_1
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; ATHLON-NEXT: ## %bb.3: ## %CF242.preheader
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; ATHLON-NEXT: fldz
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; ATHLON-NEXT: .p2align 4, 0x90
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; ATHLON-NEXT: LBB23_4: ## %CF242
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; ATHLON-NEXT: ## =>This Inner Loop Header: Depth=1
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; ATHLON-NEXT: fucomi %st(0), %st
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; ATHLON-NEXT: jp LBB23_4
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; ATHLON-NEXT: ## %bb.5: ## %CF244
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; ATHLON-NEXT: fstp %st(0)
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; ATHLON-NEXT: retl
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;
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; MCU-LABEL: test19:
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; MCU: # %bb.0: # %BB
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; MCU-NEXT: movl $-1, %ecx
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; MCU-NEXT: movb $1, %al
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; MCU-NEXT: .p2align 4, 0x90
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; MCU-NEXT: .LBB23_1: # %CF
|
||||
; MCU-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MCU-NEXT: testb %al, %al
|
||||
; MCU-NEXT: jne .LBB23_1
|
||||
; MCU-NEXT: # %bb.2: # %CF250
|
||||
; MCU-NEXT: # in Loop: Header=BB23_1 Depth=1
|
||||
; MCU-NEXT: jne .LBB23_1
|
||||
; MCU-NEXT: # %bb.3: # %CF242.preheader
|
||||
; MCU-NEXT: fldz
|
||||
; MCU-NEXT: .p2align 4, 0x90
|
||||
; MCU-NEXT: .LBB23_4: # %CF242
|
||||
; MCU-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MCU-NEXT: cmpl %eax, %ecx
|
||||
; MCU-NEXT: fucom %st(0)
|
||||
; MCU-NEXT: fnstsw %ax
|
||||
; MCU-NEXT: # kill: def $ah killed $ah killed $ax
|
||||
; MCU-NEXT: sahf
|
||||
; MCU-NEXT: jp .LBB23_4
|
||||
; MCU-NEXT: # %bb.5: # %CF244
|
||||
; MCU-NEXT: fstp %st(0)
|
||||
; MCU-NEXT: retl
|
||||
BB:
|
||||
br label %CF
|
||||
|
||||
CF:
|
||||
%Cmp10 = icmp ule i8 undef, undef
|
||||
br i1 %Cmp10, label %CF, label %CF250
|
||||
|
||||
CF250:
|
||||
%E12 = extractelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 2
|
||||
%Cmp32 = icmp ugt i1 %Cmp10, false
|
||||
br i1 %Cmp32, label %CF, label %CF242
|
||||
|
||||
CF242:
|
||||
%Cmp38 = icmp uge i32 %E12, undef
|
||||
%FC = uitofp i1 %Cmp38 to float
|
||||
%Sl59 = select i1 %Cmp32, float %FC, float undef
|
||||
%Cmp60 = fcmp ugt float undef, undef
|
||||
br i1 %Cmp60, label %CF242, label %CF244
|
||||
|
||||
CF244:
|
||||
%B122 = fadd float %Sl59, undef
|
||||
ret void
|
||||
}
|
||||
|
||||
define i16 @select_xor_1(i16 %A, i8 %cond) {
|
||||
; CHECK-LABEL: select_xor_1:
|
||||
; CHECK: ## %bb.0: ## %entry
|
||||
@ -1413,10 +1313,10 @@ define i16 @select_xor_1b(i16 %A, i8 %cond) {
|
||||
; MCU-LABEL: select_xor_1b:
|
||||
; MCU: # %bb.0: # %entry
|
||||
; MCU-NEXT: testb $1, %dl
|
||||
; MCU-NEXT: je .LBB25_2
|
||||
; MCU-NEXT: je .LBB24_2
|
||||
; MCU-NEXT: # %bb.1:
|
||||
; MCU-NEXT: xorl $43, %eax
|
||||
; MCU-NEXT: .LBB25_2: # %entry
|
||||
; MCU-NEXT: .LBB24_2: # %entry
|
||||
; MCU-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; MCU-NEXT: retl
|
||||
entry:
|
||||
@ -1483,10 +1383,10 @@ define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
|
||||
; MCU-LABEL: select_xor_2b:
|
||||
; MCU: # %bb.0: # %entry
|
||||
; MCU-NEXT: testb $1, %cl
|
||||
; MCU-NEXT: je .LBB27_2
|
||||
; MCU-NEXT: je .LBB26_2
|
||||
; MCU-NEXT: # %bb.1:
|
||||
; MCU-NEXT: xorl %edx, %eax
|
||||
; MCU-NEXT: .LBB27_2: # %entry
|
||||
; MCU-NEXT: .LBB26_2: # %entry
|
||||
; MCU-NEXT: retl
|
||||
entry:
|
||||
%and = and i8 %cond, 1
|
||||
@ -1552,10 +1452,10 @@ define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
|
||||
; MCU-LABEL: select_or_b:
|
||||
; MCU: # %bb.0: # %entry
|
||||
; MCU-NEXT: testb $1, %cl
|
||||
; MCU-NEXT: je .LBB29_2
|
||||
; MCU-NEXT: je .LBB28_2
|
||||
; MCU-NEXT: # %bb.1:
|
||||
; MCU-NEXT: orl %edx, %eax
|
||||
; MCU-NEXT: .LBB29_2: # %entry
|
||||
; MCU-NEXT: .LBB28_2: # %entry
|
||||
; MCU-NEXT: retl
|
||||
entry:
|
||||
%and = and i8 %cond, 1
|
||||
@ -1621,10 +1521,10 @@ define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
|
||||
; MCU-LABEL: select_or_1b:
|
||||
; MCU: # %bb.0: # %entry
|
||||
; MCU-NEXT: testb $1, %cl
|
||||
; MCU-NEXT: je .LBB31_2
|
||||
; MCU-NEXT: je .LBB30_2
|
||||
; MCU-NEXT: # %bb.1:
|
||||
; MCU-NEXT: orl %edx, %eax
|
||||
; MCU-NEXT: .LBB31_2: # %entry
|
||||
; MCU-NEXT: .LBB30_2: # %entry
|
||||
; MCU-NEXT: retl
|
||||
entry:
|
||||
%and = and i32 %cond, 1
|
||||
|
||||
@ -450,8 +450,6 @@ define <4 x i32> @xor_undef_lhs_vec(<4 x i32> %x) {
|
||||
define i1 @undef_operand_size_not_same_as_result() {
|
||||
; CHECK-LABEL: undef_operand_size_not_same_as_result:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: testl %eax, %eax
|
||||
; CHECK-NEXT: sete %al
|
||||
; CHECK-NEXT: retq
|
||||
%sh = shl i32 7, undef
|
||||
%cmp = icmp eq i32 0, %sh
|
||||
|
||||
@ -683,16 +683,12 @@ define <4 x i32> @test_urem_both(<4 x i32> %X) nounwind readnone {
|
||||
define <4 x i32> @test_urem_div_undef(<4 x i32> %X) nounwind readnone {
|
||||
; CHECK-SSE-LABEL: test_urem_div_undef:
|
||||
; CHECK-SSE: # %bb.0:
|
||||
; CHECK-SSE-NEXT: pxor %xmm0, %xmm0
|
||||
; CHECK-SSE-NEXT: pcmpeqd %xmm0, %xmm0
|
||||
; CHECK-SSE-NEXT: psrld $31, %xmm0
|
||||
; CHECK-SSE-NEXT: xorps %xmm0, %xmm0
|
||||
; CHECK-SSE-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX-LABEL: test_urem_div_undef:
|
||||
; CHECK-AVX: # %bb.0:
|
||||
; CHECK-AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vpsrld $31, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: retq
|
||||
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 undef, i32 5>
|
||||
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
|
||||
@ -794,16 +790,12 @@ define <4 x i32> @test_urem_comp_undef(<4 x i32> %X) nounwind readnone {
|
||||
define <4 x i32> @test_urem_both_undef(<4 x i32> %X) nounwind readnone {
|
||||
; CHECK-SSE-LABEL: test_urem_both_undef:
|
||||
; CHECK-SSE: # %bb.0:
|
||||
; CHECK-SSE-NEXT: pxor %xmm0, %xmm0
|
||||
; CHECK-SSE-NEXT: pcmpeqd %xmm0, %xmm0
|
||||
; CHECK-SSE-NEXT: psrld $31, %xmm0
|
||||
; CHECK-SSE-NEXT: xorps %xmm0, %xmm0
|
||||
; CHECK-SSE-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX-LABEL: test_urem_both_undef:
|
||||
; CHECK-AVX: # %bb.0:
|
||||
; CHECK-AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vpsrld $31, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: retq
|
||||
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 undef, i32 5>
|
||||
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 undef, i32 0, i32 0>
|
||||
|
||||
@ -1806,44 +1806,20 @@ define <4 x i16> @constant_shift_v4i16(<4 x i16> %a) nounwind {
|
||||
;
|
||||
; SSE41-LABEL: constant_shift_v4i16:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE41-NEXT: pxor %xmm0, %xmm0
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <0,1,2,3,u,u,u,u>
|
||||
; SSE41-NEXT: pcmpeqw %xmm2, %xmm0
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = <u,32768,16384,8192,u,u,u,u>
|
||||
; SSE41-NEXT: pmulhw %xmm1, %xmm3
|
||||
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm3
|
||||
; SSE41-NEXT: pcmpeqw {{.*}}(%rip), %xmm2
|
||||
; SSE41-NEXT: psraw $1, %xmm1
|
||||
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm3
|
||||
; SSE41-NEXT: movdqa %xmm3, %xmm0
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = <u,32768,16384,8192,u,u,u,u>
|
||||
; SSE41-NEXT: pmulhw %xmm0, %xmm1
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7]
|
||||
; SSE41-NEXT: psraw $1, %xmm0
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3,4,5,6,7]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: constant_shift_v4i16:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [4.1720559249406128E-309,4.1720559249406128E-309]
|
||||
; AVX1-NEXT: # xmm2 = mem[0,0]
|
||||
; AVX1-NEXT: vpcmpeqw %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm3
|
||||
; AVX1-NEXT: vpblendvb %xmm1, %xmm0, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpcmpeqw {{.*}}(%rip), %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsraw $1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: constant_shift_v4i16:
|
||||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [844433520132096,844433520132096]
|
||||
; AVX2-NEXT: vpcmpeqw %xmm1, %xmm2, %xmm1
|
||||
; AVX2-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm3
|
||||
; AVX2-NEXT: vpblendvb %xmm1, %xmm0, %xmm3, %xmm1
|
||||
; AVX2-NEXT: vpcmpeqw {{.*}}(%rip), %xmm2, %xmm2
|
||||
; AVX2-NEXT: vpsraw $1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX-LABEL: constant_shift_v4i16:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7]
|
||||
; AVX-NEXT: vpsraw $1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3,4,5,6,7]
|
||||
; AVX-NEXT: retq
|
||||
;
|
||||
; XOP-LABEL: constant_shift_v4i16:
|
||||
; XOP: # %bb.0:
|
||||
|
||||
@ -1500,32 +1500,25 @@ define <2 x i32> @constant_shift_v2i32(<2 x i32> %a) nounwind {
|
||||
define <4 x i16> @constant_shift_v4i16(<4 x i16> %a) nounwind {
|
||||
; SSE2-LABEL: constant_shift_v4i16:
|
||||
; SSE2: # %bb.0:
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = <u,32768,16384,8192,u,u,u,u>
|
||||
; SSE2-NEXT: pmulhuw %xmm0, %xmm1
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm2
|
||||
; SSE2-NEXT: pcmpeqw {{.*}}(%rip), %xmm2
|
||||
; SSE2-NEXT: pand %xmm2, %xmm0
|
||||
; SSE2-NEXT: pandn %xmm1, %xmm2
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]
|
||||
; SSE2-NEXT: movdqa %xmm1, %xmm2
|
||||
; SSE2-NEXT: pandn %xmm0, %xmm2
|
||||
; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
|
||||
; SSE2-NEXT: pand %xmm1, %xmm0
|
||||
; SSE2-NEXT: por %xmm2, %xmm0
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: constant_shift_v4i16:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE41-NEXT: pxor %xmm0, %xmm0
|
||||
; SSE41-NEXT: pcmpeqw {{.*}}(%rip), %xmm0
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <u,32768,16384,8192,u,u,u,u>
|
||||
; SSE41-NEXT: pmulhuw %xmm1, %xmm2
|
||||
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2
|
||||
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = <u,32768,16384,8192,u,u,u,u>
|
||||
; SSE41-NEXT: pmulhuw %xmm0, %xmm1
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: constant_shift_v4i16:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vpcmpeqw {{.*}}(%rip), %xmm1, %xmm1
|
||||
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm2
|
||||
; AVX-NEXT: vpblendvb %xmm1, %xmm0, %xmm2, %xmm0
|
||||
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
|
||||
; AVX-NEXT: retq
|
||||
;
|
||||
; XOP-LABEL: constant_shift_v4i16:
|
||||
@ -1535,10 +1528,8 @@ define <4 x i16> @constant_shift_v4i16(<4 x i16> %a) nounwind {
|
||||
;
|
||||
; AVX512DQ-LABEL: constant_shift_v4i16:
|
||||
; AVX512DQ: # %bb.0:
|
||||
; AVX512DQ-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX512DQ-NEXT: vpcmpeqw {{.*}}(%rip), %xmm1, %xmm1
|
||||
; AVX512DQ-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm2
|
||||
; AVX512DQ-NEXT: vpblendvb %xmm1, %xmm0, %xmm2, %xmm0
|
||||
; AVX512DQ-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; AVX512DQ-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
|
||||
; AVX512DQ-NEXT: retq
|
||||
;
|
||||
; AVX512BW-LABEL: constant_shift_v4i16:
|
||||
@ -1552,10 +1543,8 @@ define <4 x i16> @constant_shift_v4i16(<4 x i16> %a) nounwind {
|
||||
;
|
||||
; AVX512DQVL-LABEL: constant_shift_v4i16:
|
||||
; AVX512DQVL: # %bb.0:
|
||||
; AVX512DQVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX512DQVL-NEXT: vpcmpeqw {{.*}}(%rip), %xmm1, %xmm1
|
||||
; AVX512DQVL-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm2
|
||||
; AVX512DQVL-NEXT: vpblendvb %xmm1, %xmm0, %xmm2, %xmm0
|
||||
; AVX512DQVL-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; AVX512DQVL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
|
||||
; AVX512DQVL-NEXT: retq
|
||||
;
|
||||
; AVX512BWVL-LABEL: constant_shift_v4i16:
|
||||
@ -1565,12 +1554,11 @@ define <4 x i16> @constant_shift_v4i16(<4 x i16> %a) nounwind {
|
||||
;
|
||||
; X32-SSE-LABEL: constant_shift_v4i16:
|
||||
; X32-SSE: # %bb.0:
|
||||
; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = <u,32768,16384,8192,u,u,u,u>
|
||||
; X32-SSE-NEXT: pmulhuw %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: pxor %xmm2, %xmm2
|
||||
; X32-SSE-NEXT: pcmpeqw {{\.LCPI.*}}, %xmm2
|
||||
; X32-SSE-NEXT: pand %xmm2, %xmm0
|
||||
; X32-SSE-NEXT: pandn %xmm1, %xmm2
|
||||
; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]
|
||||
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
|
||||
; X32-SSE-NEXT: pandn %xmm0, %xmm2
|
||||
; X32-SSE-NEXT: pmulhuw {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: pand %xmm1, %xmm0
|
||||
; X32-SSE-NEXT: por %xmm2, %xmm0
|
||||
; X32-SSE-NEXT: retl
|
||||
%shift = lshr <4 x i16> %a, <i16 0, i16 1, i16 2, i16 3>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user