From 5202ca9718183ed07d8da53a429aa3e218be6dba Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Thu, 22 Jul 2021 13:46:19 +0000 Subject: [PATCH] [AArch64][SME] Improve diagnostic for vector select register Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D106540 --- lib/Target/AArch64/AArch64RegisterInfo.td | 4 +++- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 3 +++ test/MC/AArch64/SME/dup-diagnostics.s | 4 ++-- test/MC/AArch64/SME/ld1b-diagnostics.s | 4 ++-- test/MC/AArch64/SME/ld1d-diagnostics.s | 4 ++-- test/MC/AArch64/SME/ld1h-diagnostics.s | 4 ++-- test/MC/AArch64/SME/ld1q-diagnostics.s | 4 ++-- test/MC/AArch64/SME/ld1w-diagnostics.s | 4 ++-- test/MC/AArch64/SME/ldr-diagnostics.s | 4 ++-- test/MC/AArch64/SME/mova-diagnostics.s | 8 ++++---- test/MC/AArch64/SME/st1b-diagnostics.s | 4 ++-- test/MC/AArch64/SME/st1d-diagnostics.s | 4 ++-- test/MC/AArch64/SME/st1h-diagnostics.s | 4 ++-- test/MC/AArch64/SME/st1q-diagnostics.s | 4 ++-- test/MC/AArch64/SME/st1w-diagnostics.s | 4 ++-- test/MC/AArch64/SME/str-diagnostics.s | 4 ++-- 16 files changed, 36 insertions(+), 31 deletions(-) diff --git a/lib/Target/AArch64/AArch64RegisterInfo.td b/lib/Target/AArch64/AArch64RegisterInfo.td index bdccf11a6ca..9d689a588d3 100644 --- a/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/lib/Target/AArch64/AArch64RegisterInfo.td @@ -1352,7 +1352,9 @@ class MatrixOperand : RegisterOperand { def MatrixOp : MatrixOperand; -def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>; +def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)> { + let DiagnosticType = "InvalidMatrixIndexGPR32_12_15"; +} def MatrixIndexGPR32Op12_15 : RegisterOperand { let EncoderMethod = "encodeMatrixIndexGPR32"; } diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 6dd1e4577ec..941112b94b0 100644 --- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -5102,6 +5102,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, return Error(Loc, "invalid matrix operand, expected za[0-7].d"); case Match_InvalidMatrix: return Error(Loc, "invalid matrix operand, expected za"); + case Match_InvalidMatrixIndexGPR32_12_15: + return Error(Loc, "operand must be a register in range [w12, w15]"); default: llvm_unreachable("unexpected error code!"); } @@ -5637,6 +5639,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidMatrixTileVectorV64: case Match_InvalidMatrixTileVectorV128: case Match_InvalidSVCR: + case Match_InvalidMatrixIndexGPR32_12_15: case Match_MSR: case Match_MRS: { if (ErrorInfo >= Operands.size()) diff --git a/test/MC/AArch64/SME/dup-diagnostics.s b/test/MC/AArch64/SME/dup-diagnostics.s index ebc1fa16d75..6321f439707 100644 --- a/test/MC/AArch64/SME/dup-diagnostics.s +++ b/test/MC/AArch64/SME/dup-diagnostics.s @@ -25,12 +25,12 @@ dup p0.b, p0/z, p0[w12] // Invalid index base register register (w12-w15) dup p0.b, p0/z, p0.b[w11] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: dup p0.b, p0/z, p0.b[w11] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: dup p0.b, p0/z, p0.b[w16] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: dup p0.b, p0/z, p0.b[w16] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/ld1b-diagnostics.s b/test/MC/AArch64/SME/ld1b-diagnostics.s index 494a6fbf6b3..b614c72211c 100644 --- a/test/MC/AArch64/SME/ld1b-diagnostics.s +++ b/test/MC/AArch64/SME/ld1b-diagnostics.s @@ -22,12 +22,12 @@ ld1b {za15v.q[w12, #0]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) ld1b {za0h.b[w11, #0]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1b {za0h.b[w11, #0]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b {za0h.b[w16, #0]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1b {za0h.b[w16, #0]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/ld1d-diagnostics.s b/test/MC/AArch64/SME/ld1d-diagnostics.s index de62f8fa6f6..00cbc2f404d 100644 --- a/test/MC/AArch64/SME/ld1d-diagnostics.s +++ b/test/MC/AArch64/SME/ld1d-diagnostics.s @@ -22,12 +22,12 @@ ld1d {za3h.s[w12, #0]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) ld1d {za0h.d[w11, #0]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1d {za0h.d[w11, #0]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d {za0h.d[w16, #0]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1d {za0h.d[w16, #0]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/ld1h-diagnostics.s b/test/MC/AArch64/SME/ld1h-diagnostics.s index 3460b9d19df..679a14860a9 100644 --- a/test/MC/AArch64/SME/ld1h-diagnostics.s +++ b/test/MC/AArch64/SME/ld1h-diagnostics.s @@ -22,12 +22,12 @@ ld1h {za0.b[w12, #0]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) ld1h {za0h.h[w11, #0]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1h {za0h.h[w11, #0]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h {za0h.h[w16, #0]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1h {za0h.h[w16, #0]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/ld1q-diagnostics.s b/test/MC/AArch64/SME/ld1q-diagnostics.s index 24159c10512..06cf153db6a 100644 --- a/test/MC/AArch64/SME/ld1q-diagnostics.s +++ b/test/MC/AArch64/SME/ld1q-diagnostics.s @@ -22,12 +22,12 @@ ld1q {za7v.d[w12]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) ld1q {za0h.q[w11]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1q {za0h.q[w11]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1q {za0h.q[w16]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1q {za0h.q[w16]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/ld1w-diagnostics.s b/test/MC/AArch64/SME/ld1w-diagnostics.s index d9e3ed72121..4522871a13f 100644 --- a/test/MC/AArch64/SME/ld1w-diagnostics.s +++ b/test/MC/AArch64/SME/ld1w-diagnostics.s @@ -22,12 +22,12 @@ ld1w {za1v.h[w12, #0]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) ld1w {za0h.s[w11, #0]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1w {za0h.s[w11, #0]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w {za0h.s[w16, #0]}, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ld1w {za0h.s[w16, #0]}, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/ldr-diagnostics.s b/test/MC/AArch64/SME/ldr-diagnostics.s index 8228098a660..ca2a0824d3e 100644 --- a/test/MC/AArch64/SME/ldr-diagnostics.s +++ b/test/MC/AArch64/SME/ldr-diagnostics.s @@ -17,12 +17,12 @@ ldr za3.s[w12, #0], [x0] // Invalid vector select register (expected: w12-w15) ldr za[w11, #0], [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ldr za[w11, #0], [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldr za[w16, #0], [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: ldr za[w16, #0], [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/mova-diagnostics.s b/test/MC/AArch64/SME/mova-diagnostics.s index 31f177e35bb..119a6b170af 100644 --- a/test/MC/AArch64/SME/mova-diagnostics.s +++ b/test/MC/AArch64/SME/mova-diagnostics.s @@ -107,22 +107,22 @@ mova za[w12, #0], p0/m, z0.b // Invalid vector select register (expected: w12-w15) mova z0.h, p0/m, za0h.h[w11, #0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: mova z0.h, p0/m, za0h.h[w11, #0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: mova z0.s, p0/m, za0h.s[w16, #0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: mova z0.s, p0/m, za0h.s[w16, #0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: mova za0h.d[w11, #0], p0/m, z0.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: mova za0h.d[w11, #0], p0/m, z0.d // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: mova za0h.q[w16, #0], p0/m, z0.q -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: mova za0h.q[w16, #0], p0/m, z0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/st1b-diagnostics.s b/test/MC/AArch64/SME/st1b-diagnostics.s index 4b7417999ab..12f168ef7e4 100644 --- a/test/MC/AArch64/SME/st1b-diagnostics.s +++ b/test/MC/AArch64/SME/st1b-diagnostics.s @@ -22,12 +22,12 @@ st1b {za15v.q[w12, #0]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) st1b {za0h.b[w11, #0]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1b {za0h.b[w11, #0]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1b {za0h.b[w16, #0]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1b {za0h.b[w16, #0]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/st1d-diagnostics.s b/test/MC/AArch64/SME/st1d-diagnostics.s index a54dab2c67d..260275af8ff 100644 --- a/test/MC/AArch64/SME/st1d-diagnostics.s +++ b/test/MC/AArch64/SME/st1d-diagnostics.s @@ -22,12 +22,12 @@ st1d {za3h.s[w12, #0]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) st1d {za0h.d[w11, #0]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1d {za0h.d[w11, #0]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1d {za0h.d[w16, #0]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1d {za0h.d[w16, #0]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/st1h-diagnostics.s b/test/MC/AArch64/SME/st1h-diagnostics.s index 2c68134c6c0..448ecb5e9b7 100644 --- a/test/MC/AArch64/SME/st1h-diagnostics.s +++ b/test/MC/AArch64/SME/st1h-diagnostics.s @@ -22,12 +22,12 @@ st1h {za0.b[w12, #0]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) st1h {za0h.h[w11, #0]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1h {za0h.h[w11, #0]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1h {za0h.h[w16, #0]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1h {za0h.h[w16, #0]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/st1q-diagnostics.s b/test/MC/AArch64/SME/st1q-diagnostics.s index 4b73d6662ae..1af0d2c4292 100644 --- a/test/MC/AArch64/SME/st1q-diagnostics.s +++ b/test/MC/AArch64/SME/st1q-diagnostics.s @@ -22,12 +22,12 @@ st1q {za7v.d[w12]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) st1q {za0h.q[w11]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1q {za0h.q[w11]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1q {za0h.q[w16]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1q {za0h.q[w16]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/st1w-diagnostics.s b/test/MC/AArch64/SME/st1w-diagnostics.s index b0579de65a1..932c918368a 100644 --- a/test/MC/AArch64/SME/st1w-diagnostics.s +++ b/test/MC/AArch64/SME/st1w-diagnostics.s @@ -22,12 +22,12 @@ st1w {za1v.h[w12, #0]}, p0/z, [x0] // Invalid vector select register (expected: w12-w15) st1w {za0h.s[w11, #0]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1w {za0h.s[w11, #0]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1w {za0h.s[w16, #0]}, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: st1w {za0h.s[w16, #0]}, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SME/str-diagnostics.s b/test/MC/AArch64/SME/str-diagnostics.s index 2fd0ab090e2..33cc3c5704e 100644 --- a/test/MC/AArch64/SME/str-diagnostics.s +++ b/test/MC/AArch64/SME/str-diagnostics.s @@ -17,12 +17,12 @@ str za3.s[w12, #0], [x0] // Invalid vector select register (expected: w12-w15) str za[w11, #0], [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: str za[w11, #0], [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: str za[w16, #0], [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] // CHECK-NEXT: str za[w16, #0], [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: