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[GlobalISel] Handle non-multiples of the base type in narrowScalarAddSub
When narrowing G_ADD and G_SUB, handle types that aren't a multiple of the type we're narrowing to. This allows us to handle types like s96 on 64 bit targets. Note that the test here has a couple of dead instructions because of the way the setup legalizes. I wasn't able to come up with a way to write this test that avoids that easily. Differential Revision: https://reviews.llvm.org/D97811
This commit is contained in:
Justin Bogner
parent
5328161b2b
commit
521d48da10
@ -4885,17 +4885,6 @@ LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx,
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if (DstType.isVector())
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return UnableToLegalize;
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uint64_t SizeOp0 = DstType.getSizeInBits();
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uint64_t NarrowSize = NarrowTy.getSizeInBits();
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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// Expand in terms of carry-setting/consuming G_<Op>E instructions.
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int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
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unsigned Opcode = MI.getOpcode();
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unsigned OpO, OpE, OpF;
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switch (Opcode) {
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@ -4929,28 +4918,37 @@ LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx,
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unsigned NumDefs = MI.getNumExplicitDefs();
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Register Src1 = MI.getOperand(NumDefs).getReg();
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Register Src2 = MI.getOperand(NumDefs + 1).getReg();
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Register CarryDst;
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Register CarryDst, CarryIn;
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if (NumDefs == 2)
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CarryDst = MI.getOperand(1).getReg();
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Register CarryIn;
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if (MI.getNumOperands() == NumDefs + 3)
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CarryIn = MI.getOperand(NumDefs + 2).getReg();
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SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
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extractParts(Src1, NarrowTy, NumParts, Src1Regs);
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extractParts(Src2, NarrowTy, NumParts, Src2Regs);
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LLT RegTy = MRI.getType(MI.getOperand(0).getReg());
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LLT LeftoverTy, DummyTy;
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SmallVector<Register, 2> Src1Regs, Src2Regs, Src1Left, Src2Left, DstRegs;
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extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left);
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extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left);
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for (int i = 0; i < NumParts; ++i) {
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Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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int NarrowParts = Src1Regs.size();
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for (int I = 0, E = Src1Left.size(); I != E; ++I) {
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Src1Regs.push_back(Src1Left[I]);
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Src2Regs.push_back(Src2Left[I]);
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}
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DstRegs.reserve(Src1Regs.size());
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for (int i = 0, e = Src1Regs.size(); i != e; ++i) {
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Register DstReg =
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MRI.createGenericVirtualRegister(MRI.getType(Src1Regs[i]));
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Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
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// Forward the final carry-out to the destination register
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if (i == NumParts - 1 && CarryDst)
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if (i == e - 1 && CarryDst)
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CarryOut = CarryDst;
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if (!CarryIn) {
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MIRBuilder.buildInstr(OpO, {DstReg, CarryOut},
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{Src1Regs[i], Src2Regs[i]});
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} else if (i == NumParts - 1) {
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} else if (i == e - 1) {
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MIRBuilder.buildInstr(OpF, {DstReg, CarryOut},
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{Src1Regs[i], Src2Regs[i], CarryIn});
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} else {
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@ -4961,7 +4959,10 @@ LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx,
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DstRegs.push_back(DstReg);
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CarryIn = CarryOut;
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}
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MIRBuilder.buildMerge(DstReg, DstRegs);
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insertParts(MI.getOperand(0).getReg(), RegTy, NarrowTy,
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makeArrayRef(DstRegs).take_front(NarrowParts), LeftoverTy,
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makeArrayRef(DstRegs).drop_front(NarrowParts));
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MI.eraseFromParent();
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return Legalized;
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}
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@ -80,7 +80,7 @@ end:
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br label %block
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %{{[0-9]+}}:_(s96) = G_ADD %{{[0-9]+}}:_, %{{[0-9]+}}:_ (in function: nonpow2_add_narrowing)
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:gpr32(s32), %{{[0-9]+}}:gpr(s1) = G_UADDE %{{[0-9]+}}:gpr, %{{[0-9]+}}:gpr, %{{[0-9]+}}:gpr (in function: nonpow2_add_narrowing)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_add_narrowing
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; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_add_narrowing:
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define void @nonpow2_add_narrowing(i128 %x, i128 %y) {
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@ -73,6 +73,89 @@ body: |
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%5:_(s64) = G_ANYEXT %4(s8)
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$x0 = COPY %5(s64)
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...
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---
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name: test_scalar_add_narrowing
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_add_narrowing
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
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; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
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; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY3]](s64), 0
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; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY4]], [[COPY5]]
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; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[EXTRACT]], [[EXTRACT1]], [[UADDO1]]
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; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
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; CHECK: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[DEF]](s64), 0
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT2]](s32)
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY [[UADDO]](s64)
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; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[ANYEXT]](s64), 0
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT3]](s32)
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; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[ANYEXT1]], [[UADDE]](s32), 0
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; CHECK: $x0 = COPY [[COPY6]](s64)
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; CHECK: $x1 = COPY [[INSERT]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = COPY $x2
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%3:_(s64) = COPY $x3
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%4:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
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%5:_(s128) = G_MERGE_VALUES %2(s64), %3(s64)
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%6:_(s96) = G_TRUNC %4(s128)
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%7:_(s96) = G_TRUNC %5(s128)
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%8:_(s96) = G_ADD %6, %7
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%9:_(s128) = G_ANYEXT %8(s96)
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%10:_(s64), %11:_(s64) = G_UNMERGE_VALUES %9(s128)
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$x0 = COPY %10(s64)
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$x1 = COPY %11(s64)
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...
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---
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name: test_scalar_add_narrowing_s65
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_add_narrowing_s65
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
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; CHECK: [[EXTRACT:%[0-9]+]]:_(s1) = G_EXTRACT [[COPY1]](s64), 0
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
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; CHECK: [[EXTRACT1:%[0-9]+]]:_(s1) = G_EXTRACT [[COPY3]](s64), 0
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; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY4]], [[COPY5]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[EXTRACT]](s1)
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; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[EXTRACT1]](s1)
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; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[ZEXT]], [[ZEXT1]], [[UADDO1]]
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; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[UADDE]](s32)
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; CHECK: [[COPY6:%[0-9]+]]:_(s1) = COPY [[TRUNC]](s1)
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; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK: [[EXTRACT2:%[0-9]+]]:_(s1) = G_EXTRACT [[DEF]](s64), 0
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT2]](s1)
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; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY [[UADDO]](s64)
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; CHECK: [[EXTRACT3:%[0-9]+]]:_(s1) = G_EXTRACT [[ANYEXT]](s64), 0
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT3]](s1)
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; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[ANYEXT1]], [[COPY6]](s1), 0
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; CHECK: $x0 = COPY [[COPY7]](s64)
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; CHECK: $x1 = COPY [[INSERT]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = COPY $x2
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%3:_(s64) = COPY $x3
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%4:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
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%5:_(s128) = G_MERGE_VALUES %2(s64), %3(s64)
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%6:_(s65) = G_TRUNC %4(s128)
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%7:_(s65) = G_TRUNC %5(s128)
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%8:_(s65) = G_ADD %6, %7
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%9:_(s128) = G_ANYEXT %8(s65)
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%10:_(s64), %11:_(s64) = G_UNMERGE_VALUES %9(s128)
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$x0 = COPY %10(s64)
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$x1 = COPY %11(s64)
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...
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---
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name: test_vector_add
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