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GlobalISel: Define G_READCYCLECOUNTER

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This commit is contained in:
Matt Arsenault 2020-01-04 12:46:58 -05:00 committed by Matt Arsenault
parent ba1f4eaec6
commit 522144cc70
6 changed files with 27 additions and 0 deletions
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3
include/llvm/Support/TargetOpcodes.def
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@ -285,6 +285,9 @@ HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC)
/// INTRINSIC round intrinsic.
HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
/// INTRINSIC readcyclecounter
HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER)
/// Generic load (including anyext load)
HANDLE_TARGET_OPCODE(G_LOAD)

6
include/llvm/Target/GenericOpcodes.td
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@ -758,6 +758,12 @@ def G_INTRINSIC_ROUND : GenericInstruction {
let hasSideEffects = 0;
}
def G_READCYCLECOUNTER : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins);
let hasSideEffects = 1;
}
//------------------------------------------------------------------------------
// Memory ops
//------------------------------------------------------------------------------

1
include/llvm/Target/GlobalISel/SelectionDAGCompat.td
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@ -119,6 +119,7 @@ def : GINodeEquiv<G_FMINNUM, fminnum>;
def : GINodeEquiv<G_FMAXNUM, fmaxnum>;
def : GINodeEquiv<G_FMINNUM_IEEE, fminnum_ieee>;
def : GINodeEquiv<G_FMAXNUM_IEEE, fmaxnum_ieee>;
def : GINodeEquiv<G_READCYCLECOUNTER, readcyclecounter>;
// Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
// complications that tablegen must take care of. For example, Predicates such

2
lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -1256,6 +1256,8 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
return TargetOpcode::G_FSQRT;
case Intrinsic::trunc:
return TargetOpcode::G_INTRINSIC_TRUNC;
case Intrinsic::readcyclecounter:
return TargetOpcode::G_READCYCLECOUNTER;
}
return Intrinsic::not_intrinsic;
}

10
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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@ -2327,4 +2327,14 @@ define void @test_var_annotation(i8*, i8*, i8*, i32) {
ret void
}
declare i64 @llvm.readcyclecounter()
define i64 @test_readcyclecounter() {
; CHECK-LABEL: name: test_readcyclecounter
; CHECK: [[RES:%[0-9]+]]:_(s64) = G_READCYCLECOUNTER{{$}}
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = call i64 @llvm.readcyclecounter()
ret i64 %res
}
!0 = !{ i64 0, i64 2 }

5
test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
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@ -124,6 +124,11 @@
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_READCYCLECOUNTER (opcode 61): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_LOAD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected