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[LLVM][x86][Inline Asm] support for GCC style inline asm - Y<x> constraints
This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes D35204
Clang counterpart: D36371
Differential Revision: https://reviews.llvm.org/D36369
llvm-svn: 311644
This commit is contained in:
Coby Tayree
parent
3b2814283d
commit
5240cb1435
@ -36057,8 +36057,8 @@ X86TargetLowering::getConstraintType(StringRef Constraint) const {
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case 'v':
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case 'Y':
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case 'l':
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return C_RegisterClass;
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case 'k': // AVX512 masking registers.
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return C_RegisterClass;
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case 'a':
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case 'b':
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case 'c':
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@ -36090,8 +36090,15 @@ X86TargetLowering::getConstraintType(StringRef Constraint) const {
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switch (Constraint[1]) {
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default:
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break;
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case 'k':
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case 'z':
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case '0':
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return C_Register;
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case 'i':
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case 'm':
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case 'k':
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case 't':
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case '2':
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return C_RegisterClass;
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}
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}
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}
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@ -36139,15 +36146,42 @@ TargetLowering::ConstraintWeight
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if (type->isX86_MMXTy() && Subtarget.hasMMX())
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weight = CW_SpecificReg;
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break;
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case 'Y':
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// Other "Y<x>" (e.g. "Yk") constraints should be implemented below.
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if (constraint[1] == 'k') {
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// Support for 'Yk' (similarly to the 'k' variant below).
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weight = CW_SpecificReg;
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case 'Y': {
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unsigned Size = StringRef(constraint).size();
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// Pick 'i' as the next char as 'Yi' and 'Y' are synonymous, when matching 'Y'
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char NextChar = Size == 2 ? constraint[1] : 'i';
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if (Size > 2)
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break;
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switch (NextChar) {
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default:
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return CW_Invalid;
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// XMM0
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case 'z':
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case '0':
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if ((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1())
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return CW_SpecificReg;
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return CW_Invalid;
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// Conditional OpMask regs (AVX512)
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case 'k':
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if ((type->getPrimitiveSizeInBits() == 64) && Subtarget.hasAVX512())
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return CW_Register;
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return CW_Invalid;
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// Any MMX reg
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case 'm':
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if (type->isX86_MMXTy() && Subtarget.hasMMX())
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return weight;
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return CW_Invalid;
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// Any SSE reg when ISA >= SSE2, same as 'Y'
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case 'i':
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case 't':
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case '2':
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if (!Subtarget.hasSSE2())
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return CW_Invalid;
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break;
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}
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// Else fall through (handle "Y" constraint).
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// Fall through (handle "Y" constraint).
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LLVM_FALLTHROUGH;
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}
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case 'v':
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if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
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weight = CW_Register;
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@ -36159,7 +36193,8 @@ TargetLowering::ConstraintWeight
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break;
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case 'k':
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// Enable conditional vector operations using %k<#> registers.
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weight = CW_SpecificReg;
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if ((type->getPrimitiveSizeInBits() == 64) && Subtarget.hasAVX512())
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weight = CW_Register;
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break;
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case 'I':
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if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
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@ -36561,6 +36596,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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switch (Constraint[1]) {
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default:
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break;
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case 'i':
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case 't':
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case '2':
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return getRegForInlineAsmConstraint(TRI, "Y", VT);
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case 'm':
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if (!Subtarget.hasMMX()) break;
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return std::make_pair(0U, &X86::VR64RegClass);
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case 'z':
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case '0':
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if (!Subtarget.hasSSE1()) break;
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return std::make_pair(X86::XMM0, &X86::VR128RegClass);
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case 'k':
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// This register class doesn't allocate k0 for masked vector operation.
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if (Subtarget.hasAVX512()) { // Only supported in AVX512.
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83
test/MC/X86/x86-GCC-inline-asm-Y-constraints.ll
Normal file
83
test/MC/X86/x86-GCC-inline-asm-Y-constraints.ll
Normal file
@ -0,0 +1,83 @@
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; RUN: llc -mtriple=x86_64-apple-darwin -mcpu skx < %s | FileCheck %s
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; This test compliments the .c test under clang/test/CodeGen/. We check
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; if the inline asm constraints are respected in the generated code.
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; Function Attrs: nounwind
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define void @f_Ym(i64 %m.coerce) {
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; Any mmx regiter constraint
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; CHECK-LABEL: f_Ym:
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; CHECK: ## InlineAsm Start
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; CHECK-NEXT: movq %mm{{[0-9]+}}, %mm1
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; CHECK: ## InlineAsm End
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entry:
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%0 = tail call x86_mmx asm sideeffect "movq $0, %mm1\0A\09", "=^Ym,~{dirflag},~{fpsr},~{flags}"()
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ret void
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}
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; Function Attrs: nounwind
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define void @f_Yi(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; Any SSE register when SSE2 is enabled (GCC when inter-unit moves enabled)
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; CHECK-LABEL: f_Yi:
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; CHECK: ## InlineAsm Start
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; CHECK-NEXT: vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
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; CHECK: ## InlineAsm End
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entry:
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%0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Yi,^Yi,^Yi,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
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ret void
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}
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; Function Attrs: nounwind
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define void @f_Yt(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; Any SSE register when SSE2 is enabled
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; CHECK-LABEL: f_Yt:
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; CHECK: ## InlineAsm Start
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; CHECK-NEXT: vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
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; CHECK: ## InlineAsm End
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entry:
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%0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Yt,^Yt,^Yt,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
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ret void
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}
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; Function Attrs: nounwind
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define void @f_Y2(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; Any SSE register when SSE2 is enabled
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; CHECK-LABEL: f_Y2:
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; CHECK: ## InlineAsm Start
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; CHECK-NEXT: vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
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; CHECK: ## InlineAsm End
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entry:
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%0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Y2,^Y2,^Y2,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
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ret void
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}
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; Function Attrs: nounwind
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define void @f_Yz(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; xmm0 SSE register(GCC)
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; CHECK-LABEL: f_Yz:
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; CHECK: ## InlineAsm Start
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; CHECK-NEXT: vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm0
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; CHECK-NEXT: vpaddq %xmm0, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
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; CHECK: ## InlineAsm End
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entry:
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%0 = tail call { <4 x float>, <4 x float> } asm sideeffect "vpaddq $0,$2,$1\0A\09vpaddq $1,$0,$2\0A\09", "=^Yi,=^Yz,^Yi,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
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ret void
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}
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; Function Attrs: nounwind
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define void @f_Y0(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; xmm0 SSE register
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; CHECK-LABEL: f_Y0:
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; CHECK: ## InlineAsm Start
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; CHECK-NEXT: vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm0
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; CHECK-NEXT: vpaddq %xmm0, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
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; CHECK: ## InlineAsm End
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entry:
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%0 = tail call { <4 x float>, <4 x float> } asm sideeffect "vpaddq $0,$2,$1\0A\09vpaddq $1,$0,$2\0A\09", "=^Yi,=^Y0,^Yi,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
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ret void
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}
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