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[AArch64][SVE] Asm: Support for insert element (INSR) instructions.
Insert general purpose register into shifted vector, e.g. insr z0.s, w0 insr z0.d, x0 Insert SIMD&FP scalar register into shifted vector, e.g. insr z0.b, b0 insr z0.h, h0 insr z0.s, s0 insr z0.d, d0 llvm-svn: 336979
This commit is contained in:
Sander de Smalen
parent
20374872ff
commit
52edf6c6bd
@ -113,6 +113,8 @@ let Predicates = [HasSVE] in {
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defm SEL_ZPZZ : sve_int_sel_vvv<"sel">;
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defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
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defm INSR_ZR : sve_int_perm_insrs<"insr">;
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defm INSR_ZV : sve_int_perm_insrv<"insr">;
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def AND_PPzPP : sve_int_pred_log<0b0000, "and">;
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def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">;
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@ -658,6 +658,55 @@ multiclass sve_int_perm_tbl<string asm> {
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(!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
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}
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class sve_int_perm_insrs<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType>
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: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
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asm, "\t$Zdn, $Rm",
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"",
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[]>, Sched<[]> {
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bits<5> Rm;
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bits<5> Zdn;
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let Inst{31-24} = 0b00000101;
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let Inst{23-22} = sz8_64;
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let Inst{21-10} = 0b100100001110;
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let Inst{9-5} = Rm;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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}
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multiclass sve_int_perm_insrs<string asm> {
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def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>;
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def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>;
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def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>;
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def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
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}
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class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType>
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: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm),
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asm, "\t$Zdn, $Vm",
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"",
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[]>, Sched<[]> {
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bits<5> Vm;
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bits<5> Zdn;
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let Inst{31-24} = 0b00000101;
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let Inst{23-22} = sz8_64;
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let Inst{21-10} = 0b110100001110;
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let Inst{9-5} = Vm;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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}
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multiclass sve_int_perm_insrv<string asm> {
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def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>;
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def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>;
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def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>;
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def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Vector Select Group
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//===----------------------------------------------------------------------===//
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45
test/MC/AArch64/SVE/insr-diagnostics.s
Normal file
45
test/MC/AArch64/SVE/insr-diagnostics.s
Normal file
@ -0,0 +1,45 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid scalar operand size.
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insr z31.b, x0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: insr z31.b, x0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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insr z31.h, x0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: insr z31.h, x0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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insr z31.s, x0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: insr z31.s, x0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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insr z31.d, w0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: insr z31.d, w0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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insr z31.b, h0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: insr z31.b, h0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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insr z31.h, s0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: insr z31.h, s0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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insr z31.s, d0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: insr z31.s, d0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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insr z31.d, b0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: insr z31.d, b0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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80
test/MC/AArch64/SVE/insr.s
Normal file
80
test/MC/AArch64/SVE/insr.s
Normal file
@ -0,0 +1,80 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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insr z0.b, w0
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// CHECK-INST: insr z0.b, w0
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// CHECK-ENCODING: [0x00,0x38,0x24,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 24 05 <unknown>
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insr z0.h, w0
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// CHECK-INST: insr z0.h, w0
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// CHECK-ENCODING: [0x00,0x38,0x64,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 64 05 <unknown>
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insr z0.s, w0
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// CHECK-INST: insr z0.s, w0
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// CHECK-ENCODING: [0x00,0x38,0xa4,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 a4 05 <unknown>
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insr z0.d, x0
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// CHECK-INST: insr z0.d, x0
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// CHECK-ENCODING: [0x00,0x38,0xe4,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 e4 05 <unknown>
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insr z31.b, wzr
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// CHECK-INST: insr z31.b, wzr
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// CHECK-ENCODING: [0xff,0x3b,0x24,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b 24 05 <unknown>
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insr z31.h, wzr
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// CHECK-INST: insr z31.h, wzr
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// CHECK-ENCODING: [0xff,0x3b,0x64,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b 64 05 <unknown>
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insr z31.s, wzr
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// CHECK-INST: insr z31.s, wzr
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// CHECK-ENCODING: [0xff,0x3b,0xa4,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b a4 05 <unknown>
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insr z31.d, xzr
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// CHECK-INST: insr z31.d, xzr
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// CHECK-ENCODING: [0xff,0x3b,0xe4,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b e4 05 <unknown>
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insr z31.b, b31
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// CHECK-INST: insr z31.b, b31
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// CHECK-ENCODING: [0xff,0x3b,0x34,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b 34 05 <unknown>
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insr z31.h, h31
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// CHECK-INST: insr z31.h, h31
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// CHECK-ENCODING: [0xff,0x3b,0x74,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b 74 05 <unknown>
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insr z31.s, s31
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// CHECK-INST: insr z31.s, s31
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// CHECK-ENCODING: [0xff,0x3b,0xb4,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b b4 05 <unknown>
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insr z31.d, d31
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// CHECK-INST: insr z31.d, d31
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// CHECK-ENCODING: [0xff,0x3b,0xf4,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b f4 05 <unknown>
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