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[Hexagon] Fix isNVStorable flag in .td files
An upper half and a double word cannot be used as value sources in a new-value store. llvm-svn: 250867
This commit is contained in:
Krzysztof Parzyszek
parent
cc2c07a96e
commit
52f05db67a
@ -3303,7 +3303,8 @@ class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
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!if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
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!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0})));
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let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1));
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let IClass = 0b1010;
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@ -3322,7 +3323,7 @@ class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
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//===----------------------------------------------------------------------===//
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let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
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class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
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bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew>
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: STInst <(outs IntRegs:$_dst_),
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(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
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!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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@ -3341,7 +3342,8 @@ class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
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!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0})));
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let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1));
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let isPredicatedNew = isPredNew;
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let isPredicatedFalse = isPredNot;
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@ -3404,7 +3406,6 @@ def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>;
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//===----------------------------------------------------------------------===//
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// Template class for post increment stores with register offset.
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//===----------------------------------------------------------------------===//
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let isNVStorable = 1 in
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class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
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MemAccessSize AccessSz, bit isHalf = 0>
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: STInst <(outs IntRegs:$_dst_),
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@ -3416,6 +3417,9 @@ class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
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bits<5> src3;
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let accessSize = AccessSz;
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if(!eq(mnemonic,"memd"), 0, !if(isHalf,0,1));
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let IClass = 0b1010;
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let Inst{27-24} = 0b1101;
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@ -3430,12 +3434,11 @@ def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
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def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
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def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
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def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
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def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
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let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
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class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<3>MajOp, bit isH = 0>
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bits<3> MajOp, bit isH = 0>
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: STInst <(outs),
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(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
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mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
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@ -3455,6 +3458,8 @@ class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
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!if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
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!if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
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/* s11_0Ext */ src2{10-0})));
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
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let IClass = 0b1010;
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let Inst{27} = 0b0;
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@ -3494,7 +3499,10 @@ class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
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!if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
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!if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
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/* u6_0Ext */ src3{5-0})));
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let IClass = 0b0100;
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
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let IClass = 0b0100;
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let Inst{27} = 0b0;
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let Inst{26} = PredNot;
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@ -3508,7 +3516,7 @@ class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
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let Inst{1-0} = src1;
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}
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let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
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let isExtendable = 1, hasSideEffects = 0 in
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multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
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Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
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@ -3665,7 +3673,7 @@ def S2_allocframe: ST0Inst <
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// S2_storer[bhwdf]_pci: Store byte/half/word/double.
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// S2_storer[bhwdf]_pci -> S2_storerbnew_pci
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let Uses = [CS], isNVStorable = 1 in
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let Uses = [CS] in
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class T_store_pci <string mnemonic, RegisterClass RC,
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Operand Imm, bits<4>MajOp,
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MemAccessSize AlignSize, string RegSrc = "Rt">
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@ -3679,6 +3687,8 @@ class T_store_pci <string mnemonic, RegisterClass RC,
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bits<1> Mu;
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bits<5> Rt;
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let accessSize = AlignSize;
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let isNVStorable = !if(!eq(mnemonic,"memd"), 0,
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!if(!eq(RegSrc,"Rt.h"), 0, 1));
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let IClass = 0b1010;
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let Inst{27-25} = 0b100;
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@ -3696,15 +3706,15 @@ class T_store_pci <string mnemonic, RegisterClass RC,
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}
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def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
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ByteAccess>;
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ByteAccess>;
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def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
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HalfWordAccess>;
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HalfWordAccess>;
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def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
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HalfWordAccess, "Rt.h">;
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HalfWordAccess, "Rt.h">;
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def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
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WordAccess>;
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WordAccess>;
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def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
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DoubleWordAccess>;
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DoubleWordAccess>;
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let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
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class T_storenew_pci <string mnemonic, Operand Imm,
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@ -3762,7 +3772,7 @@ def S2_storerd_pci_pseudo : T_store_pci_pseudo <"memd", DoubleRegs>;
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//===----------------------------------------------------------------------===//
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// Circular stores with auto-increment register
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//===----------------------------------------------------------------------===//
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let Uses = [CS], isNVStorable = 1 in
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let Uses = [CS] in
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class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
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MemAccessSize AlignSize, string RegSrc = "Rt">
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: STInst <(outs IntRegs:$_dst_),
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@ -3775,6 +3785,8 @@ class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
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bits<5> Rt;
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let accessSize = AlignSize;
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let isNVStorable = !if(!eq(mnemonic,"memd"), 0,
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!if(!eq(RegSrc,"Rt.h"), 0, 1));
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let IClass = 0b1010;
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let Inst{27-25} = 0b100;
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@ -684,7 +684,7 @@ def: Pat<(i64 (zext (i32 IntRegs:$src1))),
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// Template class for store instructions with Absolute set addressing mode.
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//===----------------------------------------------------------------------===//
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let isExtended = 1, opExtendable = 1, opExtentBits = 6,
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addrMode = AbsoluteSet, isNVStorable = 1 in
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addrMode = AbsoluteSet in
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class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
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bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
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: STInst<(outs IntRegs:$dst),
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@ -696,6 +696,9 @@ class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
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let accessSize = AccessSz;
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let BaseOpcode = BaseOp#"_AbsSet";
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
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let IClass = 0b1010;
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let Inst{27-24} = 0b1011;
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@ -750,7 +753,7 @@ let mayStore = 1, addrMode = AbsoluteSet in {
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}
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let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
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addrMode = BaseLongOffset, AddedComplexity = 40 in
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addrMode = BaseLongOffset, AddedComplexity = 40 in
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class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
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bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
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: STInst<(outs),
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@ -766,6 +769,10 @@ class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
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let accessSize = AccessSz;
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let CextOpcode = CextOp;
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let BaseOpcode = CextOp#"_shl";
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
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let IClass = 0b1010;
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let Inst{27-24} =0b1101;
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@ -856,6 +863,9 @@ class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
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bits<2> u2;
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bits<5> Rt;
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
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let IClass = 0b0011;
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let Inst{27-24} = 0b1011;
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@ -888,6 +898,8 @@ class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
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let isPredicatedFalse = isNot;
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let isPredicatedNew = isPredNew;
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
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let IClass = 0b0011;
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@ -3306,7 +3318,7 @@ let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
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// Template class for non predicated store instructions with
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// GP-Relative or absolute addressing.
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
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let hasSideEffects = 0, isPredicable = 1 in
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class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
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: STInst<(outs), (ins AddrOp:$addr, RC:$src),
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@ -3321,6 +3333,9 @@ class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
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!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
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!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
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/* u16_0Imm */ addr{15-0})));
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
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let IClass = 0b0100;
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let Inst{27} = 1;
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let Inst{26-25} = offsetBits{15-14};
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@ -3337,8 +3352,7 @@ class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
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// Template class for predicated store instructions with
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// GP-Relative or absolute addressing.
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
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opExtendable = 1 in
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let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in
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class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
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bit isHalf, bit isNot, bit isNew>
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: STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
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@ -3351,6 +3365,8 @@ class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
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let isPredicatedNew = isNew;
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let isPredicatedFalse = isNot;
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// Store upper-half and store doubleword cannot be NV.
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let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
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let IClass = 0b1010;
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