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[ARM] Don't expand sdiv when optimising for minsize
Don't expand SDIV with an immediate that is a power of 2 if we optimise for minimum code size. For example: sdiv %1, i32 4 gets expanded to a sequence of 3 instructions, but this is suboptimal for minimum code size so instead we just generate a MOV and a SDIV if integer division is supported. Differential Revision: https://reviews.llvm.org/D54546 llvm-svn: 347965
This commit is contained in:
Sjoerd Meijer
parent
ff5a1e1583
commit
532a78148a
@ -7794,6 +7794,50 @@ SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
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return LowerCallTo(CLI).first;
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}
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// This is a code size optimisation: return the original SDIV node to
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// DAGCombiner when we don't want to expand SDIV into a sequence of
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// instructions, and an empty node otherwise which will cause the
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// SDIV to be expanded in DAGCombine.
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SDValue
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ARMTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
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SelectionDAG &DAG,
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SmallVectorImpl<SDNode *> &Created) const {
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// TODO: Support SREM
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if (N->getOpcode() != ISD::SDIV)
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return SDValue();
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const auto &ST = static_cast<const ARMSubtarget&>(DAG.getSubtarget());
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const auto &MF = DAG.getMachineFunction();
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const bool MinSize = MF.getFunction().optForMinSize();
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const bool HasDivide = ST.isThumb() ? ST.hasDivideInThumbMode()
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: ST.hasDivideInARMMode();
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// Don't touch vector types; rewriting this may lead to scalarizing
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// the int divs.
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if (N->getOperand(0).getValueType().isVector())
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return SDValue();
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// Bail if MinSize is not set, and also for both ARM and Thumb mode we need
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// hwdiv support for this to be really profitable.
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if (!(MinSize && HasDivide))
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return SDValue();
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// ARM mode is a bit simpler than Thumb: we can handle large power
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// of 2 immediates with 1 mov instruction; no further checks required,
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// just return the sdiv node.
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if (!ST.isThumb())
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return SDValue(N, 0);
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// In Thumb mode, immediates larger than 128 need a wide 4-byte MOV,
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// and thus lose the code size benefits of a MOVS that requires only 2.
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// TargetTransformInfo and 'getIntImmCodeSizeCost' could be helpful here,
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// but as it's doing exactly this, it's not worth the trouble to get TTI.
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if (Divisor.sgt(128))
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return SDValue();
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return SDValue(N, 0);
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}
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SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
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bool Signed) const {
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assert(Op.getValueType() == MVT::i32 &&
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@ -694,6 +694,9 @@ class VectorType;
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unsigned getRegisterByName(const char* RegName, EVT VT,
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SelectionDAG &DAG) const override;
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SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
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SmallVectorImpl<SDNode *> &Created) const override;
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/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
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/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
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/// expanded to FMAs when this method returns true, otherwise fmuladd is
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79
test/CodeGen/ARM/sdiv-pow2-arm-size.ll
Normal file
79
test/CodeGen/ARM/sdiv-pow2-arm-size.ll
Normal file
@ -0,0 +1,79 @@
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; RUN: llc -mtriple=armv7a -mattr=+hwdiv-arm %s -o - | FileCheck %s --check-prefixes=CHECK,DIV
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; RUN: llc -mtriple=armv7a -mattr=-hwdiv-arm %s -o - | FileCheck %s --check-prefixes=CHECK,NODIV
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; Check SREM
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define dso_local i32 @test_rem(i32 %F) local_unnamed_addr #0 {
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; CHECK-LABEL: test_rem
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; CHECK: asr r1, r0, #31
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; CHECK-NEXT: add r1, r0, r1, lsr #30
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; CHECK-NEXT: bic r1, r1, #3
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; CHECK-NEXT: sub r0, r0, r1
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entry:
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%div = srem i32 %F, 4
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ret i32 %div
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}
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; Try an i16 sdiv, with a small immediate.
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define dso_local signext i16 @f0(i16 signext %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f0
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; DIV: mov r1, #2
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; DIV-NEXT: sdiv r0, r0, r1
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; DIV-NEXT: sxth r0, r0
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; DIV-NEXT: bx lr
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; NODIV: uxth r1, r0
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; NODIV-NEXT: add r0, r0, r1, lsr #15
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; NODIV-NEXT: sxth r0, r0
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; NODIV-NEXT: asr r0, r0, #1
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; NODIV-NEXT: bx lr
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entry:
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%0 = sdiv i16 %F, 2
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ret i16 %0
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}
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; Try an i32 sdiv, with a small immediate.
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define dso_local i32 @f1(i32 %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f1
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; DIV: mov r1, #4
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; DIV-NEXT: sdiv r0, r0, r1
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; DIV-NEXT: bx lr
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; NODIV: asr r1, r0, #31
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; NODIV-NEXT: add r0, r0, r1, lsr #30
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; NODIV-NEXT: asr r0, r0, #2
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; NODIV-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 4
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ret i32 %div
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}
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; Try a large power of 2 immediate, which should also be materialised with 1
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; move immediate instruction.
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define dso_local i32 @f2(i32 %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f2
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; DIV: mov r1, #131072
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; DIV-NEXT: sdiv r0, r0, r1
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; DIV-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 131072
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ret i32 %div
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}
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; MinSize not set, so should expand to the faster but longer sequence.
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define dso_local i32 @f3(i32 %F) {
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; CHECK-LABEL: f3
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; CHECK: asr r1, r0, #31
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; CHECK-NEXT: add r0, r0, r1, lsr #30
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; CHECK-NEXT: asr r0, r0, #2
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; CHECK-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 4
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ret i32 %div
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}
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attributes #0 = { minsize norecurse nounwind optsize readnone }
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105
test/CodeGen/ARM/sdiv-pow2-thumb-size.ll
Normal file
105
test/CodeGen/ARM/sdiv-pow2-thumb-size.ll
Normal file
@ -0,0 +1,105 @@
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; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s --check-prefixes=CHECK,T2
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; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefixes=CHECK,T2
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; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s --check-prefixes=CHECK,T1
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; RUN: llc -mtriple=thumbv7em %s -o - | FileCheck %s --check-prefixes=CHECK,T2
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; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefixes=V6M
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; Armv6m targets don't have a sdiv instruction, so sdiv should not appear at
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; all in the output:
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; V6M: .file {{.*}}
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; V6M-NOT: sdiv
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; V6M-NOT: idiv
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; Test sdiv i16
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define dso_local signext i16 @f0(i16 signext %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f0
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; CHECK: movs r1, #2
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; CHECK-NEXT: sdiv r0, r0, r1
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; CHECK-NEXT: sxth r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = sdiv i16 %F, 2
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ret i16 %0
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}
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; Same as above, but now with i32
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define dso_local i32 @f1(i32 %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f1
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; CHECK: movs r1, #4
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; CHECK-NEXT: sdiv r0, r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 4
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ret i32 %div
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}
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; The immediate is not a power of 2, so we expect a sdiv.
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define dso_local i32 @f2(i32 %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f2
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; CHECK: movs r1, #5
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; CHECK-NEXT: sdiv r0, r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 5
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ret i32 %div
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}
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; Try a larger power of 2 immediate: immediates larger than
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; 128 don't give any code size savings.
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define dso_local i32 @f3(i32 %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f3
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; CHECK-NOT: sdiv
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entry:
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%div = sdiv i32 %F, 256
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ret i32 %div
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}
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attributes #0 = { minsize norecurse nounwind optsize readnone }
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; These functions don't have the minsize attribute set, so should not lower
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; the sdiv to sdiv, but to the faster instruction sequence.
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define dso_local signext i16 @f4(i16 signext %F) {
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; T2-LABEL: f4
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; T2: uxth r1, r0
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; T2-NEXT: add.w r0, r0, r1, lsr #15
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; T2-NEXT: sxth r0, r0
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; T2-NEXT: asrs r0, r0, #1
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; T2-NEXT: bx lr
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; T1-LABEL: f4
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; T1: uxth r1, r0
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; T1-NEXT: lsrs r1, r1, #15
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; T1-NEXT: adds r0, r0, r1
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; T1-NEXT: sxth r0, r0
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; T1-NEXT: asrs r0, r0, #1
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; T1-NEXT: bx lr
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entry:
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%0 = sdiv i16 %F, 2
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ret i16 %0
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}
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define dso_local i32 @f5(i32 %F) {
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; T2-LABEL: f5
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; T2: asrs r1, r0, #31
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; T2-NEXT: add.w r0, r0, r1, lsr #30
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; T2-NEXT: asrs r0, r0, #2
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; T2-NEXT: bx lr
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; T1-LABEL: f5
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; T1: asrs r1, r0, #31
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; T1-NEXT: lsrs r1, r1, #30
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; T1-NEXT: adds r0, r0, r1
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; T1-NEXT: asrs r0, r0, #2
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; T1-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 4
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ret i32 %div
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}
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