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[X86] Use WriteResPair for WriteIDiv to cleanup sched defs. NFCI.

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llvm-svn: 328460
This commit is contained in:
Simon Pilgrim 2018-03-25 20:16:53 +00:00
parent 529713cc08
commit 534ee4515a
4 changed files with 10 additions and 37 deletions
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10
lib/Target/X86/X86SchedHaswell.td
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@ -122,15 +122,7 @@ defm : HWWriteResPair<WriteJump, [HWPort06], 1>;
def : WriteRes<WriteLEA, [HWPort15]>;
// This is quite rough, latency depends on the dividend.
def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
let Latency = 25;
let ResourceCycles = [1, 10];
}
def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
let Latency = 29;
let ResourceCycles = [1, 1, 10];
}
defm : HWWriteResPair<WriteIDiv, [HWPort0, HWDivider], 25, [1,10], 1, 4>;
// Scalar and vector floating point.
def : WriteRes<WriteFStore, [HWPort237, HWPort4]>;
def : WriteRes<WriteFLoad, [HWPort23]> { let Latency = 5; }

14
lib/Target/X86/X86SchedSkylakeClient.td
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@ -61,6 +61,8 @@ def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
// 60 Entry Unified Scheduler
def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
SKLPort5, SKLPort6, SKLPort7]> {
@ -103,17 +105,9 @@ def : WriteRes<WriteRMW, [SKLPort4]>;
// Arithmetic.
defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.
defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.
def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
def : WriteRes<WriteIDiv, [SKLPort0, SKLDivider]> { // Integer division.
let Latency = 25;
let ResourceCycles = [1, 10];
}
def : WriteRes<WriteIDivLd, [SKLPort23, SKLPort0, SKLDivider]> {
let Latency = 29;
let ResourceCycles = [1, 1, 10];
}
defm : SKLWriteResPair<WriteIDiv, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>; // Integer division.
def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
// Integer shifts and rotates.

14
lib/Target/X86/X86SchedSkylakeServer.td
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@ -61,6 +61,8 @@ def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
// 60 Entry Unified Scheduler
def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
SKXPort5, SKXPort6, SKXPort7]> {
@ -103,17 +105,9 @@ def : WriteRes<WriteRMW, [SKXPort4]>;
// Arithmetic.
defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
defm : SKXWriteResPair<WriteIMul, [SKXPort1], 3>; // Integer multiplication.
def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
def : WriteRes<WriteIDiv, [SKXPort0, SKXDivider]> { // Integer division.
let Latency = 25;
let ResourceCycles = [1, 10];
}
def : WriteRes<WriteIDivLd, [SKXPort23, SKXPort0, SKXDivider]> {
let Latency = 29;
let ResourceCycles = [1, 1, 10];
}
defm : SKXWriteResPair<WriteIDiv, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>; // Integer division.
def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
// Integer shifts and rotates.

9
lib/Target/X86/X86ScheduleSLM.td
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@ -98,14 +98,7 @@ defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>;
def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
// This is quite rough, latency depends on the dividend.
def : WriteRes<WriteIDiv, [SLM_IEC_RSV01, SLMDivider]> {
let Latency = 25;
let ResourceCycles = [1, 25];
}
def : WriteRes<WriteIDivLd, [SLM_MEC_RSV, SLM_IEC_RSV01, SLMDivider]> {
let Latency = 29;
let ResourceCycles = [1, 1, 25];
}
defm : SLMWriteResPair<WriteIDiv, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
// Scalar and vector floating point.
def : WriteRes<WriteFStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>;