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[X86] Use WriteResPair for WriteIDiv to cleanup sched defs. NFCI.
llvm-svn: 328460
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@ -122,15 +122,7 @@ defm : HWWriteResPair<WriteJump, [HWPort06], 1>;
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def : WriteRes<WriteLEA, [HWPort15]>;
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def : WriteRes<WriteLEA, [HWPort15]>;
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// This is quite rough, latency depends on the dividend.
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// This is quite rough, latency depends on the dividend.
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def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
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defm : HWWriteResPair<WriteIDiv, [HWPort0, HWDivider], 25, [1,10], 1, 4>;
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let Latency = 25;
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let ResourceCycles = [1, 10];
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}
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def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
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let Latency = 29;
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let ResourceCycles = [1, 1, 10];
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}
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// Scalar and vector floating point.
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// Scalar and vector floating point.
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def : WriteRes<WriteFStore, [HWPort237, HWPort4]>;
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def : WriteRes<WriteFStore, [HWPort237, HWPort4]>;
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def : WriteRes<WriteFLoad, [HWPort23]> { let Latency = 5; }
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def : WriteRes<WriteFLoad, [HWPort23]> { let Latency = 5; }
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@ -61,6 +61,8 @@ def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
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def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
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def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
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def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
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def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
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def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
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// 60 Entry Unified Scheduler
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// 60 Entry Unified Scheduler
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def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
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def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
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SKLPort5, SKLPort6, SKLPort7]> {
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SKLPort5, SKLPort6, SKLPort7]> {
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@ -103,17 +105,9 @@ def : WriteRes<WriteRMW, [SKLPort4]>;
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// Arithmetic.
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// Arithmetic.
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defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.
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defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.
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defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.
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defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.
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def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
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defm : SKLWriteResPair<WriteIDiv, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>; // Integer division.
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def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
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def : WriteRes<WriteIDiv, [SKLPort0, SKLDivider]> { // Integer division.
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let Latency = 25;
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let ResourceCycles = [1, 10];
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}
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def : WriteRes<WriteIDivLd, [SKLPort23, SKLPort0, SKLDivider]> {
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let Latency = 29;
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let ResourceCycles = [1, 1, 10];
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}
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def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
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def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
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def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
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// Integer shifts and rotates.
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// Integer shifts and rotates.
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@ -61,6 +61,8 @@ def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
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def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
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def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
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def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
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def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
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def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
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// 60 Entry Unified Scheduler
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// 60 Entry Unified Scheduler
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def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
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def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
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SKXPort5, SKXPort6, SKXPort7]> {
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SKXPort5, SKXPort6, SKXPort7]> {
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@ -103,17 +105,9 @@ def : WriteRes<WriteRMW, [SKXPort4]>;
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// Arithmetic.
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// Arithmetic.
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defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
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defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
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defm : SKXWriteResPair<WriteIMul, [SKXPort1], 3>; // Integer multiplication.
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defm : SKXWriteResPair<WriteIMul, [SKXPort1], 3>; // Integer multiplication.
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def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
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defm : SKXWriteResPair<WriteIDiv, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>; // Integer division.
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def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
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def : WriteRes<WriteIDiv, [SKXPort0, SKXDivider]> { // Integer division.
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let Latency = 25;
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let ResourceCycles = [1, 10];
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}
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def : WriteRes<WriteIDivLd, [SKXPort23, SKXPort0, SKXDivider]> {
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let Latency = 29;
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let ResourceCycles = [1, 1, 10];
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}
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def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
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def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
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def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
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// Integer shifts and rotates.
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// Integer shifts and rotates.
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@ -98,14 +98,7 @@ defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>;
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def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
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def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
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// This is quite rough, latency depends on the dividend.
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// This is quite rough, latency depends on the dividend.
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def : WriteRes<WriteIDiv, [SLM_IEC_RSV01, SLMDivider]> {
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defm : SLMWriteResPair<WriteIDiv, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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let Latency = 25;
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let ResourceCycles = [1, 25];
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}
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def : WriteRes<WriteIDivLd, [SLM_MEC_RSV, SLM_IEC_RSV01, SLMDivider]> {
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let Latency = 29;
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let ResourceCycles = [1, 1, 25];
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}
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// Scalar and vector floating point.
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// Scalar and vector floating point.
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def : WriteRes<WriteFStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>;
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def : WriteRes<WriteFStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>;
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