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Revert "AArch64: Use CMP;CCMP sequences for and/or/setcc trees."
The patch triggers a miscompile on SPEC 2006 403.gcc with the (ref) 200.i and scilab.i inputs. I opened PR23866 to track analysis of this. This reverts commit r238793. llvm-svn: 239880
This commit is contained in:
Matthias Braun
parent
2549bed7f1
commit
53746a75e4
@ -76,9 +76,6 @@ cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
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cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
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cl::init(false));
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/// Value type used for condition codes.
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static const MVT MVT_CC = MVT::i32;
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AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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const AArch64Subtarget &STI)
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: TargetLowering(TM), Subtarget(&STI) {
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@ -810,9 +807,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
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case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
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case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
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case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
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case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
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case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
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case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
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case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
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case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
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@ -1171,133 +1165,10 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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LHS = LHS.getOperand(0);
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}
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return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
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return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
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.getValue(1);
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}
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static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
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ISD::CondCode CC, SDValue CCOp,
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SDValue Condition, unsigned NZCV,
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SDLoc DL, SelectionDAG &DAG) {
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unsigned Opcode = 0;
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if (LHS.getValueType().isFloatingPoint())
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Opcode = AArch64ISD::FCCMP;
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else if (RHS.getOpcode() == ISD::SUB) {
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SDValue SubOp0 = RHS.getOperand(0);
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if (const ConstantSDNode *SubOp0C = dyn_cast<ConstantSDNode>(SubOp0))
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if (SubOp0C->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
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// See emitComparison() on why we can only do this for SETEQ and SETNE.
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Opcode = AArch64ISD::CCMN;
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RHS = RHS.getOperand(1);
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}
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}
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if (Opcode == 0)
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Opcode = AArch64ISD::CCMP;
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SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
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return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
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}
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/// Returns true if @p Val is a tree of AND/OR/SETCC operations.
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static bool isConjunctionDisjunctionTree(const SDValue Val, unsigned Depth) {
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if (!Val.hasOneUse())
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return false;
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if (Val->getOpcode() == ISD::SETCC)
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return true;
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// Protect against stack overflow.
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if (Depth > 1000)
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return false;
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if (Val->getOpcode() == ISD::AND || Val->getOpcode() == ISD::OR) {
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SDValue O0 = Val->getOperand(0);
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SDValue O1 = Val->getOperand(1);
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return isConjunctionDisjunctionTree(O0, Depth+1) &&
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isConjunctionDisjunctionTree(O1, Depth+1);
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}
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return false;
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}
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/// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
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/// of CCMP/CFCMP ops. For example (SETCC_0 & SETCC_1) with condition cond0 and
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/// cond1 can be transformed into "CMP; CCMP" with CCMP executing on cond_0
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/// and setting flags to inversed(cond_1) otherwise.
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/// This recursive function produces DAG nodes that produce condition flags
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/// suitable to determine the truth value of @p Val (which is AND/OR/SETCC)
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/// by testing the result for the condition set to @p OutCC. If @p Negate is
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/// set the opposite truth value is produced. If @p CCOp and @p Condition are
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/// given then conditional comparison are created so that false is reported
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/// when they are false.
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static SDValue emitConjunctionDisjunctionTree(
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SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate,
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SDValue CCOp = SDValue(), AArch64CC::CondCode Condition = AArch64CC::AL) {
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assert(isConjunctionDisjunctionTree(Val, 0));
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// We're at a tree leaf, produce a c?f?cmp.
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unsigned Opcode = Val->getOpcode();
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if (Opcode == ISD::SETCC) {
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SDValue LHS = Val->getOperand(0);
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SDValue RHS = Val->getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
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bool isInteger = LHS.getValueType().isInteger();
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if (Negate)
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CC = getSetCCInverse(CC, isInteger);
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SDLoc DL(Val);
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// Determine OutCC and handle FP special case.
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if (isInteger) {
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OutCC = changeIntCCToAArch64CC(CC);
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} else {
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assert(LHS.getValueType().isFloatingPoint());
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AArch64CC::CondCode ExtraCC;
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changeFPCCToAArch64CC(CC, OutCC, ExtraCC);
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// Surpisingly some floating point conditions can't be tested with a
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// single condition code. Construct an additional comparison in this case.
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// See comment below on how we deal with OR conditions.
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if (ExtraCC != AArch64CC::AL) {
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SDValue ExtraCmp;
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if (!CCOp.getNode())
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ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
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else {
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SDValue ConditionOp = DAG.getConstant(Condition, DL, MVT_CC);
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// Note that we want the inverse of ExtraCC, so NZCV is not inversed.
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unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(ExtraCC);
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ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
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NZCV, DL, DAG);
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}
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CCOp = ExtraCmp;
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Condition = AArch64CC::getInvertedCondCode(ExtraCC);
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OutCC = AArch64CC::getInvertedCondCode(OutCC);
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}
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}
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// Produce a normal comparison if we are first in the chain
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if (!CCOp.getNode())
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return emitComparison(LHS, RHS, CC, DL, DAG);
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// Otherwise produce a ccmp.
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SDValue ConditionOp = DAG.getConstant(Condition, DL, MVT_CC);
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AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
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unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
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return emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp, NZCV, DL,
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DAG);
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}
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// Construct comparison sequence for the left hand side.
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SDValue LHS = Val->getOperand(0);
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SDValue RHS = Val->getOperand(1);
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// We can only implement AND-like behaviour here, but negation is free. So we
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// use (not (and (not x) (not y))) to implement (or x y).
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bool isOr = Val->getOpcode() == ISD::OR;
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assert((isOr || Val->getOpcode() == ISD::AND) && "Should have AND or OR.");
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Negate ^= isOr;
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AArch64CC::CondCode RHSCC;
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SDValue CmpR =
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emitConjunctionDisjunctionTree(DAG, RHS, RHSCC, isOr, CCOp, Condition);
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SDValue CmpL =
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emitConjunctionDisjunctionTree(DAG, LHS, OutCC, isOr, CmpR, RHSCC);
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if (Negate)
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OutCC = AArch64CC::getInvertedCondCode(OutCC);
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return CmpL;
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}
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static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
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SDValue Cmp;
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@ -1356,55 +1227,47 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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}
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}
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}
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// The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
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// For the i8 operand, the largest immediate is 255, so this can be easily
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// encoded in the compare instruction. For the i16 operand, however, the
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// largest immediate cannot be encoded in the compare.
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// Therefore, use a sign extending load and cmn to avoid materializing the -1
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// constant. For example,
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// movz w1, #65535
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// ldrh w0, [x0, #0]
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// cmp w0, w1
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// >
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// ldrsh w0, [x0, #0]
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// cmn w0, #1
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// Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
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// if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
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// both the LHS and RHS are truely zero extended and to make sure the
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// transformation is profitable.
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if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
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const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
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// The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
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// For the i8 operand, the largest immediate is 255, so this can be easily
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// encoded in the compare instruction. For the i16 operand, however, the
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// largest immediate cannot be encoded in the compare.
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// Therefore, use a sign extending load and cmn to avoid materializing the
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// -1 constant. For example,
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// movz w1, #65535
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// ldrh w0, [x0, #0]
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// cmp w0, w1
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// >
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// ldrsh w0, [x0, #0]
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// cmn w0, #1
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// Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
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// if and only if (sext LHS) == (sext RHS). The checks are in place to
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// ensure both the LHS and RHS are truely zero extended and to make sure the
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// transformation is profitable.
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if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
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cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
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cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
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LHS.getNode()->hasNUsesOfValue(1, 0)) {
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int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
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if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
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SDValue SExt =
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DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
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DAG.getValueType(MVT::i16));
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Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
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RHS.getValueType()),
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CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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goto CreateCCNode;
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if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
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isa<LoadSDNode>(LHS)) {
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if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
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cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
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LHS.getNode()->hasNUsesOfValue(1, 0)) {
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int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
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if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
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SDValue SExt =
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DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
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DAG.getValueType(MVT::i16));
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Cmp = emitComparison(SExt,
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DAG.getConstant(ValueofRHS, dl,
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RHS.getValueType()),
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CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
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return Cmp;
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}
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}
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}
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if ((RHSC->isNullValue() || RHSC->isOne()) &&
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isConjunctionDisjunctionTree(LHS, 0)) {
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bool Negate = (CC == ISD::SETNE) ^ RHSC->isNullValue();
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Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC, Negate);
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goto CreateCCNode;
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}
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}
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Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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CreateCCNode:
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AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
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AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
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return Cmp;
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}
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@ -9269,8 +9132,3 @@ bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
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Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
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return Ty->isArrayTy();
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}
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bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,
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EVT) const {
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return false;
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}
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@ -58,11 +58,6 @@ enum NodeType : unsigned {
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SBCS,
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ANDS,
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// Conditional compares. Operands: left,right,falsecc,cc,flags
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CCMP,
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CCMN,
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FCCMP,
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// Floating point comparison
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FCMP,
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@ -513,8 +508,6 @@ private:
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bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
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CallingConv::ID CallConv,
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bool isVarArg) const override;
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bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
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};
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namespace AArch64 {
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@ -525,13 +525,6 @@ def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
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let ParserMatchClass = Imm0_31Operand;
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}
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// True if the 32-bit immediate is in the range [0,31]
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def imm32_0_31 : Operand<i32>, ImmLeaf<i32, [{
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return ((uint64_t)Imm) < 32;
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}]> {
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let ParserMatchClass = Imm0_31Operand;
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}
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// imm0_15 predicate - True if the immediate is in the range [0,15]
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def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
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return ((uint64_t)Imm) < 16;
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@ -549,9 +542,7 @@ def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
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// imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]
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def imm32_0_15 : Operand<i32>, ImmLeaf<i32, [{
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return ((uint32_t)Imm) < 16;
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}]> {
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let ParserMatchClass = Imm0_15Operand;
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}
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}]>;
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// An arithmetic shifter operand:
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// {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
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@ -2077,12 +2068,9 @@ multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
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//---
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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class BaseCondComparisonImm<bit op, RegisterClass regtype, ImmLeaf immtype,
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string mnemonic, SDNode OpNode>
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: I<(outs), (ins regtype:$Rn, immtype:$imm, imm32_0_15:$nzcv, ccode:$cond),
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mnemonic, "\t$Rn, $imm, $nzcv, $cond", "",
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[(set NZCV, (OpNode regtype:$Rn, immtype:$imm, (i32 imm:$nzcv),
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(i32 imm:$cond), NZCV))]>,
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class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
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: I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
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asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
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Sched<[WriteI, ReadI]> {
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let Uses = [NZCV];
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let Defs = [NZCV];
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@ -2102,13 +2090,19 @@ class BaseCondComparisonImm<bit op, RegisterClass regtype, ImmLeaf immtype,
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let Inst{3-0} = nzcv;
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}
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multiclass CondSetFlagsImm<bit op, string asm> {
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def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
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let Inst{31} = 0;
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}
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def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
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let Inst{31} = 1;
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}
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}
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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class BaseCondComparisonReg<bit op, RegisterClass regtype, string mnemonic,
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SDNode OpNode>
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: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
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mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "",
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[(set NZCV, (OpNode regtype:$Rn, regtype:$Rm, (i32 imm:$nzcv),
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(i32 imm:$cond), NZCV))]>,
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class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
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: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
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asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
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Sched<[WriteI, ReadI, ReadI]> {
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let Uses = [NZCV];
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let Defs = [NZCV];
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@ -2128,19 +2122,11 @@ class BaseCondComparisonReg<bit op, RegisterClass regtype, string mnemonic,
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let Inst{3-0} = nzcv;
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}
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multiclass CondComparison<bit op, string mnemonic, SDNode OpNode> {
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// immediate operand variants
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def Wi : BaseCondComparisonImm<op, GPR32, imm32_0_31, mnemonic, OpNode> {
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multiclass CondSetFlagsReg<bit op, string asm> {
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def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
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let Inst{31} = 0;
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}
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def Xi : BaseCondComparisonImm<op, GPR64, imm0_31, mnemonic, OpNode> {
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let Inst{31} = 1;
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}
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// register operand variants
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def Wr : BaseCondComparisonReg<op, GPR32, mnemonic, OpNode> {
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let Inst{31} = 0;
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}
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def Xr : BaseCondComparisonReg<op, GPR64, mnemonic, OpNode> {
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def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
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let Inst{31} = 1;
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}
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}
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@ -3948,14 +3934,11 @@ multiclass FPComparison<bit signalAllNans, string asm,
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//---
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
|
||||
class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
|
||||
string mnemonic, list<dag> pat>
|
||||
: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
|
||||
mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "", pat>,
|
||||
class BaseFPCondComparison<bit signalAllNans,
|
||||
RegisterClass regtype, string asm>
|
||||
: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
|
||||
asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
|
||||
Sched<[WriteFCmp]> {
|
||||
let Uses = [NZCV];
|
||||
let Defs = [NZCV];
|
||||
|
||||
bits<5> Rn;
|
||||
bits<5> Rm;
|
||||
bits<4> nzcv;
|
||||
@ -3971,18 +3954,16 @@ class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
|
||||
let Inst{3-0} = nzcv;
|
||||
}
|
||||
|
||||
multiclass FPCondComparison<bit signalAllNans, string mnemonic,
|
||||
SDPatternOperator OpNode = null_frag> {
|
||||
def Srr : BaseFPCondComparison<signalAllNans, FPR32, mnemonic,
|
||||
[(set NZCV, (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm), (i32 imm:$nzcv),
|
||||
(i32 imm:$cond), NZCV))]> {
|
||||
multiclass FPCondComparison<bit signalAllNans, string asm> {
|
||||
let Defs = [NZCV], Uses = [NZCV] in {
|
||||
def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
|
||||
let Inst{22} = 0;
|
||||
}
|
||||
def Drr : BaseFPCondComparison<signalAllNans, FPR64, mnemonic,
|
||||
[(set NZCV, (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm), (i32 imm:$nzcv),
|
||||
(i32 imm:$cond), NZCV))]> {
|
||||
|
||||
def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
|
||||
let Inst{22} = 1;
|
||||
}
|
||||
} // Defs = [NZCV], Uses = [NZCV]
|
||||
}
|
||||
|
||||
//---
|
||||
|
||||
@ -66,20 +66,6 @@ def SDT_AArch64CSel : SDTypeProfile<1, 4,
|
||||
SDTCisSameAs<0, 2>,
|
||||
SDTCisInt<3>,
|
||||
SDTCisVT<4, i32>]>;
|
||||
def SDT_AArch64CCMP : SDTypeProfile<1, 5,
|
||||
[SDTCisVT<0, i32>,
|
||||
SDTCisInt<1>,
|
||||
SDTCisSameAs<1, 2>,
|
||||
SDTCisInt<3>,
|
||||
SDTCisInt<4>,
|
||||
SDTCisVT<5, i32>]>;
|
||||
def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
|
||||
[SDTCisVT<0, i32>,
|
||||
SDTCisFP<1>,
|
||||
SDTCisSameAs<1, 2>,
|
||||
SDTCisInt<3>,
|
||||
SDTCisInt<4>,
|
||||
SDTCisVT<5, i32>]>;
|
||||
def SDT_AArch64FCmp : SDTypeProfile<0, 2,
|
||||
[SDTCisFP<0>,
|
||||
SDTCisSameAs<0, 1>]>;
|
||||
@ -174,10 +160,6 @@ def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
|
||||
def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
|
||||
def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
|
||||
|
||||
def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
|
||||
def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
|
||||
def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
|
||||
|
||||
def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
|
||||
|
||||
def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
|
||||
@ -1036,10 +1018,13 @@ def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
|
||||
def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Conditional comparison instructions.
|
||||
// Conditionally set flags instructions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
|
||||
defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
|
||||
defm CCMN : CondSetFlagsImm<0, "ccmn">;
|
||||
defm CCMP : CondSetFlagsImm<1, "ccmp">;
|
||||
|
||||
defm CCMN : CondSetFlagsReg<0, "ccmn">;
|
||||
defm CCMP : CondSetFlagsReg<1, "ccmp">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Conditional select instructions.
|
||||
@ -2569,7 +2554,7 @@ defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
defm FCCMPE : FPCondComparison<1, "fccmpe">;
|
||||
defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
|
||||
defm FCCMP : FPCondComparison<0, "fccmp">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating point conditional select instruction.
|
||||
|
||||
@ -287,43 +287,3 @@ sw.bb.i.i:
|
||||
%code1.i.i.phi.trans.insert = getelementptr inbounds %str1, %str1* %0, i64 0, i32 0, i32 0, i64 16
|
||||
br label %sw.bb.i.i
|
||||
}
|
||||
|
||||
; CHECK-LABEL: select_and
|
||||
define i64 @select_and(i32 %v1, i32 %v2, i64 %a, i64 %b) {
|
||||
; CHECK: cmp
|
||||
; CHECK: ccmp{{.*}}, #0, ne
|
||||
; CHECK: csel{{.*}}, lt
|
||||
%1 = icmp slt i32 %v1, %v2
|
||||
%2 = icmp ne i32 5, %v2
|
||||
%3 = and i1 %1, %2
|
||||
%sel = select i1 %3, i64 %a, i64 %b
|
||||
ret i64 %sel
|
||||
}
|
||||
|
||||
; CHECK-LABEL: select_or
|
||||
define i64 @select_or(i32 %v1, i32 %v2, i64 %a, i64 %b) {
|
||||
; CHECK: cmp
|
||||
; CHECK: ccmp{{.*}}, #8, eq
|
||||
; CHECK: csel{{.*}}, lt
|
||||
%1 = icmp slt i32 %v1, %v2
|
||||
%2 = icmp ne i32 5, %v2
|
||||
%3 = or i1 %1, %2
|
||||
%sel = select i1 %3, i64 %a, i64 %b
|
||||
ret i64 %sel
|
||||
}
|
||||
|
||||
; CHECK-LABEL: select_complicated
|
||||
define i16 @select_complicated(double %v1, double %v2, i16 %a, i16 %b) {
|
||||
; CHECK: fcmp
|
||||
; CHECK: fccmp{{.*}}, #4, ne
|
||||
; CHECK: fccmp{{.*}}, #1, ne
|
||||
; CHECK: fccmp{{.*}}, #4, vc
|
||||
; CEHCK: csel{{.*}}, eq
|
||||
%1 = fcmp one double %v1, %v2
|
||||
%2 = fcmp oeq double %v2, 13.0
|
||||
%3 = fcmp oeq double %v1, 42.0
|
||||
%or0 = or i1 %2, %3
|
||||
%or1 = or i1 %1, %or0
|
||||
%sel = select i1 %or1, i16 %a, i16 %b
|
||||
ret i16 %sel
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user