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[AVX512] Fix load opcode for fast isel.

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Differential Revision: http://reviews.llvm.org/D21067

llvm-svn: 272006
This commit is contained in:
Igor Breger 2016-06-07 13:08:45 +00:00
parent f4980a0fe0
commit 53dd84b6c0
2 changed files with 22 additions and 1 deletions
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2
lib/Target/X86/X86FastISel.cpp
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@ -452,7 +452,7 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM,
assert(Subtarget->hasAVX512()); assert(Subtarget->hasAVX512());
// Note: There are a lot more choices based on type with AVX-512, but // Note: There are a lot more choices based on type with AVX-512, but
// there's really no advantage when the load isn't masked. // there's really no advantage when the load isn't masked.
Opc = (Alignment >= 64) ? X86::VMOVDQA64Zmr : X86::VMOVDQU64Zmr; Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm;
RC = &X86::VR512RegClass; RC = &X86::VR512RegClass;
break; break;
} }

21
test/CodeGen/X86/fast-isel-vecload.ll
View File

@ -1,5 +1,6 @@
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE --check-prefix=ALL ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE --check-prefix=ALL
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX --check-prefix=ALL ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX --check-prefix=ALL
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx512f < %s | FileCheck %s --check-prefix=KNL
; Verify that fast-isel knows how to select aligned/unaligned vector loads. ; Verify that fast-isel knows how to select aligned/unaligned vector loads.
; Also verify that the selected load instruction is in the correct domain. ; Also verify that the selected load instruction is in the correct domain.
@ -183,3 +184,23 @@ entry:
%0 = load <2 x double>, <2 x double>* %V %0 = load <2 x double>, <2 x double>* %V
ret <2 x double> %0 ret <2 x double> %0
} }
define <8 x i64> @test_v8i64_alignment(<8 x i64>* %V) {
; KNL-LABEL: test_v8i64_alignment:
; KNL: # BB#0: # %entry
; KNL-NEXT: vmovdqa64 (%rdi), %zmm0
; KNL-NEXT: retq
entry:
%0 = load <8 x i64>, <8 x i64>* %V, align 64
ret <8 x i64> %0
}
define <8 x i64> @test_v8i64(<8 x i64>* %V) {
; KNL-LABEL: test_v8i64:
; KNL: # BB#0: # %entry
; KNL-NEXT: vmovdqu64 (%rdi), %zmm0
; KNL-NEXT: retq
entry:
%0 = load <8 x i64>, <8 x i64>* %V, align 4
ret <8 x i64> %0
}