mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
llvm-svn: 123619
This commit is contained in:
Evan Cheng
parent
77e381e302
commit
53ec6fc591
@ -20,6 +20,7 @@
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#include "ARMBaseRegisterInfo.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMMCExpr.h"
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#include "ARMTargetMachine.h"
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#include "ARMTargetObjectFile.h"
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#include "InstPrinter/ARMInstPrinter.h"
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@ -537,6 +538,25 @@ getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
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return MCSymbolRefExpr::VK_None;
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}
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MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
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bool isIndirect = Subtarget->isTargetDarwin() &&
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Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
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if (!isIndirect)
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return Mang->getSymbol(GV);
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// FIXME: Remove this when Darwin transition to @GOT like syntax.
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MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
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MachineModuleInfoMachO &MMIMachO =
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MMI->getObjFileInfo<MachineModuleInfoMachO>();
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MachineModuleInfoImpl::StubValueTy &StubSym =
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GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
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MMIMachO.getGVStubEntry(MCSym);
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if (StubSym.getPointer() == 0)
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StubSym = MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
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return MCSym;
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}
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void ARMAsmPrinter::
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EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
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@ -553,23 +573,7 @@ EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
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} else if (ACPV->isGlobalValue()) {
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const GlobalValue *GV = ACPV->getGV();
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bool isIndirect = Subtarget->isTargetDarwin() &&
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Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
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if (!isIndirect)
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MCSym = Mang->getSymbol(GV);
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else {
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// FIXME: Remove this when Darwin transition to @GOT like syntax.
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MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
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MachineModuleInfoMachO &MMIMachO =
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MMI->getObjFileInfo<MachineModuleInfoMachO>();
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MachineModuleInfoImpl::StubValueTy &StubSym =
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GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
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MMIMachO.getGVStubEntry(MCSym);
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if (StubSym.getPointer() == 0)
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StubSym = MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
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}
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MCSym = GetARMGVSymbol(GV);
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} else {
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assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
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MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
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@ -737,7 +741,8 @@ void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
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}
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void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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default: break;
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case ARM::t2ADDrSPi:
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case ARM::t2ADDrSPi12:
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@ -858,6 +863,61 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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}
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return;
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}
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case ARM::MOVi16_pic_ga:
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case ARM::t2MOVi16_pic_ga: {
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MCInst TmpInst;
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TmpInst.setOpcode(Opc == ARM::MOVi16_pic_ga ? ARM::MOVi16 : ARM::t2MOVi16);
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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const GlobalValue *GV = MI->getOperand(1).getGlobal();
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MCSymbol *GVSym = GetARMGVSymbol(GV);
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const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
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MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
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getFunctionNumber(), MI->getOperand(2).getImm(),
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OutContext);
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const MCExpr *LabelSymExpr = MCSymbolRefExpr::Create(LabelSym, OutContext);
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const MCExpr *PCRelExpr =
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ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
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MCBinaryExpr::CreateAdd(LabelSymExpr,
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MCConstantExpr::Create(4, OutContext),
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OutContext), OutContext), OutContext);
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TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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// Add 's' bit operand (always reg0 for this)
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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return;
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}
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case ARM::MOVTi16_pic_ga:
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case ARM::t2MOVTi16_pic_ga: {
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MCInst TmpInst;
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TmpInst.setOpcode(Opc==ARM::MOVTi16_pic_ga ? ARM::MOVTi16 : ARM::t2MOVTi16);
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
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const GlobalValue *GV = MI->getOperand(2).getGlobal();
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MCSymbol *GVSym = GetARMGVSymbol(GV);
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const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
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MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
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getFunctionNumber(), MI->getOperand(3).getImm(),
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OutContext);
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const MCExpr *LabelSymExpr = MCSymbolRefExpr::Create(LabelSym, OutContext);
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const MCExpr *PCRelExpr =
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ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
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MCBinaryExpr::CreateAdd(LabelSymExpr,
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MCConstantExpr::Create(4, OutContext),
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OutContext), OutContext), OutContext);
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TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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// Add 's' bit operand (always reg0 for this)
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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return;
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}
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case ARM::tPICADD: {
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// This is a pseudo op for a label + instruction sequence, which looks like:
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// LPC0:
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@ -101,6 +101,8 @@ public:
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MCSymbol *GetARMSJLJEHLabel(void) const;
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MCSymbol *GetARMGVSymbol(const GlobalValue *GV);
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/// EmitMachineConstantPoolValue - Print a machine constantpool value to
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/// the .s file.
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virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV);
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@ -185,6 +185,18 @@ namespace ARMII {
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/// higher 16 bit of the address. Used only via movt instruction.
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MO_HI16,
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/// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
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/// relocation containing lower 16 bit of the PC relative address of the
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/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
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/// Used only via movw instruction.
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MO_LO16_NONLAZY_PIC,
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/// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
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/// relocation containing lower 16 bit of the PC relative address of the
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/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
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/// Used only via movt instruction.
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MO_HI16_NONLAZY_PIC,
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/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
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/// call operand.
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MO_PLT
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@ -561,8 +561,14 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
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case ARMII::SizeSpecial: {
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switch (Opc) {
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case ARM::MOVi16_pic_ga:
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case ARM::MOVTi16_pic_ga:
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case ARM::t2MOVi16_pic_ga:
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case ARM::t2MOVTi16_pic_ga:
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return 4;
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case ARM::MOVi32imm:
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case ARM::t2MOVi32imm:
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case ARM::MOV_pic_ga:
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return 8;
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case ARM::CONSTPOOL_ENTRY:
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// If this machine instr is a constant pool entry, its size is recorded as
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@ -977,7 +983,7 @@ static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
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ARMConstantPoolValue *ACPV =
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static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
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unsigned PCLabelId = AFI->createConstPoolEntryUId();
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unsigned PCLabelId = AFI->createPICLabelUId();
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ARMConstantPoolValue *NewCPV = 0;
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// FIXME: The below assumes PIC relocation model and that the function
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// is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
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@ -316,7 +316,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
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}
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/// The next UID to take is the first unused one.
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AFI->initConstPoolEntryUId(CPEMIs.size());
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AFI->initPICLabelUId(CPEMIs.size());
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// Do the initial scan of the function, building up information about the
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// sizes of each block, the location of all the water, and finding all of the
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@ -1245,7 +1245,7 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &MF,
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// No existing clone of this CPE is within range.
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// We will be generating a new clone. Get a UID for it.
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unsigned ID = AFI->createConstPoolEntryUId();
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unsigned ID = AFI->createPICLabelUId();
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// Look for water where we can place this CPE.
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MachineBasicBlock *NewIsland = MF.CreateMachineBasicBlock();
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@ -765,13 +765,16 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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case ARM::MOVi32imm:
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case ARM::MOVCCi32imm:
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case ARM::MOV_pic_ga:
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case ARM::t2MOVi32imm:
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case ARM::t2MOVCCi32imm: {
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case ARM::t2MOVCCi32imm:
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case ARM::t2MOV_pic_ga: {
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
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unsigned DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
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bool isPIC_GA = (Opcode == ARM::t2MOV_pic_ga || Opcode == ARM::MOV_pic_ga);
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const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
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MachineInstrBuilder LO16, HI16;
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@ -798,14 +801,24 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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break;
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}
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bool isThumb =
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(Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm);
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unsigned LO16Opc = 0;
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unsigned HI16Opc = 0;
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if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
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LO16Opc = ARM::t2MOVi16;
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HI16Opc = ARM::t2MOVTi16;
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} else if (Opcode == ARM::MOV_pic_ga) {
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LO16Opc = ARM::MOVi16_pic_ga;
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HI16Opc = ARM::MOVTi16_pic_ga;
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} else if (Opcode == ARM::t2MOV_pic_ga) {
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LO16Opc = ARM::t2MOVi16_pic_ga;
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HI16Opc = ARM::t2MOVTi16_pic_ga;
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} else {
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LO16Opc = ARM::MOVi16;
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HI16Opc = ARM::MOVTi16;
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}
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LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(isThumb ? ARM::t2MOVi16 : ARM::MOVi16),
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DstReg);
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HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(isThumb ? ARM::t2MOVTi16 : ARM::MOVTi16))
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LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
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HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstReg);
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@ -815,16 +828,30 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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unsigned Hi16 = (Imm >> 16) & 0xffff;
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LO16 = LO16.addImm(Lo16);
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HI16 = HI16.addImm(Hi16);
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} else if (isPIC_GA) {
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unsigned LabelId = MI.getOperand(2).getImm();
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const GlobalValue *GV = MO.getGlobal();
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unsigned TF = MO.getTargetFlags();
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LO16 = LO16.addGlobalAddress(GV, MO.getOffset(),
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TF | ARMII::MO_LO16_NONLAZY_PIC)
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.addImm(LabelId);
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HI16 = HI16.addGlobalAddress(GV, MO.getOffset(),
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TF | ARMII::MO_HI16_NONLAZY_PIC)
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.addImm(LabelId);
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} else {
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const GlobalValue *GV = MO.getGlobal();
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unsigned TF = MO.getTargetFlags();
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LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
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HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
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}
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(*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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(*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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if (!isPIC_GA) {
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LO16.addImm(Pred).addReg(PredReg);
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HI16.addImm(Pred).addReg(PredReg);
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}
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TransferImpOps(MI, LO16, HI16);
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MI.eraseFromParent();
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break;
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@ -517,7 +517,7 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
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// Grab index.
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unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
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unsigned Id = AFI->createConstPoolEntryUId();
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unsigned Id = AFI->createPICLabelUId();
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ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
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ARMCP::CPValue, PCAdj);
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unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
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@ -127,8 +127,7 @@ public:
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SDValue &Offset);
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bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
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bool SelectAddrModePC(SDValue N, SDValue &Offset,
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SDValue &Label);
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bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
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// Thumb Addressing Modes:
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bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
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@ -734,6 +734,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case ARMISD::Wrapper: return "ARMISD::Wrapper";
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case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
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case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
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case ARMISD::CALL: return "ARMISD::CALL";
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case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
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@ -1315,7 +1316,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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const GlobalValue *GV = G->getGlobal();
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// Create a constant pool entry for the callee address
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unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
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unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
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ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
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ARMPCLabelIndex,
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ARMCP::CPValue, 0);
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@ -1330,7 +1331,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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const char *Sym = S->getSymbol();
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// Create a constant pool entry for the callee address
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unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
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unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
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ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
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Sym, ARMPCLabelIndex, 0);
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// Get the address of the callee into a register
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@ -1352,7 +1353,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
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// tBX takes a register source operand.
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if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
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unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
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unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
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ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
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ARMPCLabelIndex,
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ARMCP::CPValue, 4);
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@ -1381,7 +1382,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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// tBX takes a register source operand.
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const char *Sym = S->getSymbol();
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if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
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unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
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unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
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ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
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Sym, ARMPCLabelIndex, 4);
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SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
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@ -1808,7 +1809,7 @@ SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
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CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
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} else {
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unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
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ARMPCLabelIndex = AFI->createConstPoolEntryUId();
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ARMPCLabelIndex = AFI->createPICLabelUId();
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ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
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ARMCP::CPBlockAddress,
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PCAdj);
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@ -1833,7 +1834,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
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MachineFunction &MF = DAG.getMachineFunction();
|
||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
|
||||
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
|
||||
ARMConstantPoolValue *CPV =
|
||||
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
|
||||
ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
|
||||
@ -1878,7 +1879,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
|
||||
if (GV->isDeclaration()) {
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
|
||||
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
|
||||
// Initial exec model.
|
||||
unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
|
||||
ARMConstantPoolValue *CPV =
|
||||
@ -1949,10 +1950,13 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
|
||||
Result = DAG.getLoad(PtrVT, dl, Chain, Result,
|
||||
MachinePointerInfo::getGOT(), false, false, 0);
|
||||
return Result;
|
||||
} else {
|
||||
}
|
||||
|
||||
// If we have T2 ops, we can materialize the address directly via movt/movw
|
||||
// pair. This is always cheaper.
|
||||
if (Subtarget->useMovt()) {
|
||||
// FIXME: Once remat is capable of dealing with instructions with register
|
||||
// operands, expand this into two nodes.
|
||||
return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
|
||||
DAG.getTargetGlobalAddress(GV, dl, PtrVT));
|
||||
} else {
|
||||
@ -1962,23 +1966,39 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
|
||||
MachinePointerInfo::getConstantPool(),
|
||||
false, false, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
unsigned ARMPCLabelIndex = 0;
|
||||
EVT PtrVT = getPointerTy();
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
||||
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
|
||||
if (Subtarget->useMovt()) {
|
||||
// FIXME: Once remat is capable of dealing with instructions with register
|
||||
// operands, expand this into two nodes.
|
||||
if (RelocM != Reloc::PIC_)
|
||||
return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
|
||||
DAG.getTargetGlobalAddress(GV, dl, PtrVT));
|
||||
|
||||
// FIXME: Not a constant pool!
|
||||
unsigned PICLabelIndex = AFI->createPICLabelUId();
|
||||
SDValue PICLabel = DAG.getConstant(PICLabelIndex, MVT::i32);
|
||||
SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT,
|
||||
DAG.getTargetGlobalAddress(GV, dl, PtrVT),
|
||||
PICLabel);
|
||||
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
|
||||
}
|
||||
|
||||
unsigned ARMPCLabelIndex = 0;
|
||||
SDValue CPAddr;
|
||||
if (RelocM == Reloc::Static)
|
||||
if (RelocM == Reloc::Static) {
|
||||
CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
|
||||
else {
|
||||
ARMPCLabelIndex = AFI->createConstPoolEntryUId();
|
||||
} else {
|
||||
ARMPCLabelIndex = AFI->createPICLabelUId();
|
||||
unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
|
||||
ARMConstantPoolValue *CPV =
|
||||
new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
|
||||
@ -2009,7 +2029,7 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
|
||||
"GLOBAL OFFSET TABLE not implemented for non-ELF targets");
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
|
||||
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
|
||||
EVT PtrVT = getPointerTy();
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
|
||||
@ -2062,7 +2082,7 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
|
||||
case Intrinsic::eh_sjlj_lsda: {
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
|
||||
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
|
||||
EVT PtrVT = getPointerTy();
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
|
||||
|
||||
@ -34,6 +34,8 @@ namespace llvm {
|
||||
|
||||
Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
|
||||
// TargetExternalSymbol, and TargetGlobalAddress.
|
||||
WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
|
||||
// PIC mode.
|
||||
WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
|
||||
|
||||
CALL, // Function call.
|
||||
|
||||
@ -70,6 +70,7 @@ def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
|
||||
// Node definitions.
|
||||
def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
|
||||
def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
|
||||
def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntBinOp>;
|
||||
|
||||
def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
|
||||
[SDNPHasChain, SDNPOutGlue]>;
|
||||
@ -1930,7 +1931,10 @@ def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
|
||||
let Inst{25} = 1;
|
||||
}
|
||||
|
||||
let Constraints = "$src = $Rd" in
|
||||
def MOVi16_pic_ga : PseudoInst<(outs GPR:$Rd),
|
||||
(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
|
||||
|
||||
let Constraints = "$src = $Rd" in {
|
||||
def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
|
||||
DPFrm, IIC_iMOVi,
|
||||
"movt", "\t$Rd, $imm",
|
||||
@ -1947,6 +1951,11 @@ def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
|
||||
let Inst{25} = 1;
|
||||
}
|
||||
|
||||
def MOVTi16_pic_ga : PseudoInst<(outs GPR:$Rd),
|
||||
(ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
|
||||
|
||||
} // Constraints
|
||||
|
||||
def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
|
||||
Requires<[IsARM, HasV6T2]>;
|
||||
|
||||
@ -3363,11 +3372,17 @@ def Int_eh_sjlj_dispatchsetup :
|
||||
// This is a single pseudo instruction, the benefit is that it can be remat'd
|
||||
// as a single unit instead of having to handle reg inputs.
|
||||
// FIXME: Remove this when we can do generalized remat.
|
||||
let isReMaterializable = 1, isMoveImm = 1 in
|
||||
let isReMaterializable = 1, isMoveImm = 1 in {
|
||||
def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
|
||||
[(set GPR:$dst, (arm_i32imm:$src))]>,
|
||||
Requires<[IsARM]>;
|
||||
|
||||
def MOV_pic_ga : PseudoInst<(outs GPR:$dst),
|
||||
(ins i32imm:$addr, pclabel:$id), IIC_iMOVix2,
|
||||
[(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr, imm:$id))]>,
|
||||
Requires<[IsARM, UseMovt]>;
|
||||
} // isReMaterializable = 1, isMoveImm = 1 in
|
||||
|
||||
// ConstantPool, GlobalAddress, and JumpTable
|
||||
def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
|
||||
Requires<[IsARM, DontUseMovt]>;
|
||||
|
||||
@ -1696,7 +1696,10 @@ def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi,
|
||||
let Inst{7-0} = imm{7-0};
|
||||
}
|
||||
|
||||
let Constraints = "$src = $Rd" in
|
||||
def t2MOVi16_pic_ga : PseudoInst<(outs rGPR:$Rd),
|
||||
(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
|
||||
|
||||
let Constraints = "$src = $Rd" in {
|
||||
def t2MOVTi16 : T2I<(outs rGPR:$Rd),
|
||||
(ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi,
|
||||
"movt", "\t$Rd, $imm",
|
||||
@ -1718,6 +1721,10 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd),
|
||||
let Inst{7-0} = imm{7-0};
|
||||
}
|
||||
|
||||
def t2MOVTi16_pic_ga : PseudoInst<(outs rGPR:$Rd),
|
||||
(ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
|
||||
} // Constraints
|
||||
|
||||
def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -3209,11 +3216,17 @@ def t2RFEIA : T2RFE<0b111010011001,
|
||||
// 32-bit immediate using movw + movt.
|
||||
// This is a single pseudo instruction to make it re-materializable.
|
||||
// FIXME: Remove this when we can do generalized remat.
|
||||
let isReMaterializable = 1, isMoveImm = 1 in
|
||||
let isReMaterializable = 1, isMoveImm = 1 in {
|
||||
def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
|
||||
[(set rGPR:$dst, (i32 imm:$src))]>,
|
||||
Requires<[IsThumb, HasV6T2]>;
|
||||
|
||||
def t2MOV_pic_ga : PseudoInst<(outs rGPR:$dst),
|
||||
(ins i32imm:$addr, pclabel:$id), IIC_iMOVix2,
|
||||
[(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr, imm:$id))]>,
|
||||
Requires<[IsThumb2, UseMovt]>;
|
||||
} // isReMaterializable = 1, isMoveImm = 1 in
|
||||
|
||||
// ConstantPool, GlobalAddress, and JumpTable
|
||||
def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
|
||||
Requires<[IsThumb2, DontUseMovt]>;
|
||||
|
||||
@ -105,7 +105,7 @@ namespace llvm {
|
||||
/// model is PIC.
|
||||
void Initialize(const MachineFunction &MF, bool isPIC) {
|
||||
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
ConstPoolId2AddrMap.resize(AFI->getNumConstPoolEntries());
|
||||
ConstPoolId2AddrMap.resize(AFI->getNumPICLabels());
|
||||
JumpTableId2AddrMap.resize(AFI->getNumJumpTables());
|
||||
IsPIC = isPIC;
|
||||
}
|
||||
|
||||
@ -87,7 +87,7 @@ class ARMFunctionInfo : public MachineFunctionInfo {
|
||||
///
|
||||
unsigned JumpTableUId;
|
||||
|
||||
unsigned ConstPoolEntryUId;
|
||||
unsigned PICLabelUId;
|
||||
|
||||
/// VarArgsFrameIndex - FrameIndex for start of varargs area.
|
||||
int VarArgsFrameIndex;
|
||||
@ -104,8 +104,8 @@ public:
|
||||
FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
|
||||
GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
|
||||
GPRCS1Frames(0), GPRCS2Frames(0), DPRCSFrames(0),
|
||||
JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0),
|
||||
HasITBlocks(false) {}
|
||||
JumpTableUId(0), PICLabelUId(0),
|
||||
VarArgsFrameIndex(0), HasITBlocks(false) {}
|
||||
|
||||
explicit ARMFunctionInfo(MachineFunction &MF) :
|
||||
isThumb(MF.getTarget().getSubtarget<ARMSubtarget>().isThumb()),
|
||||
@ -116,8 +116,8 @@ public:
|
||||
GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
|
||||
GPRCS1Frames(32), GPRCS2Frames(32), DPRCSFrames(32),
|
||||
SpilledCSRegs(MF.getTarget().getRegisterInfo()->getNumRegs()),
|
||||
JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0),
|
||||
HasITBlocks(false) {}
|
||||
JumpTableUId(0), PICLabelUId(0),
|
||||
VarArgsFrameIndex(0), HasITBlocks(false) {}
|
||||
|
||||
bool isThumbFunction() const { return isThumb; }
|
||||
bool isThumb1OnlyFunction() const { return isThumb && !hasThumb2; }
|
||||
@ -227,16 +227,16 @@ public:
|
||||
return JumpTableUId;
|
||||
}
|
||||
|
||||
void initConstPoolEntryUId(unsigned UId) {
|
||||
ConstPoolEntryUId = UId;
|
||||
void initPICLabelUId(unsigned UId) {
|
||||
PICLabelUId = UId;
|
||||
}
|
||||
|
||||
unsigned getNumConstPoolEntries() const {
|
||||
return ConstPoolEntryUId;
|
||||
unsigned getNumPICLabels() const {
|
||||
return PICLabelUId;
|
||||
}
|
||||
|
||||
unsigned createConstPoolEntryUId() {
|
||||
return ConstPoolEntryUId++;
|
||||
unsigned createPICLabelUId() {
|
||||
return PICLabelUId++;
|
||||
}
|
||||
|
||||
int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
|
||||
|
||||
@ -25,8 +25,7 @@ ReserveR9("arm-reserve-r9", cl::Hidden,
|
||||
cl::desc("Reserve R9, making it unavailable as GPR"));
|
||||
|
||||
static cl::opt<bool>
|
||||
UseMOVT("arm-use-movt",
|
||||
cl::init(true), cl::Hidden);
|
||||
UseMOVT("arm-darwin-use-movt", cl::init(false), cl::Hidden);
|
||||
|
||||
static cl::opt<bool>
|
||||
StrictAlign("arm-strict-align", cl::Hidden,
|
||||
@ -45,7 +44,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
|
||||
, NoARM(false)
|
||||
, PostRAScheduler(false)
|
||||
, IsR9Reserved(ReserveR9)
|
||||
, UseMovt(UseMOVT)
|
||||
, UseMovt(false)
|
||||
, HasFP16(false)
|
||||
, HasD16(false)
|
||||
, HasHardwareDivide(false)
|
||||
@ -147,8 +146,16 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
|
||||
if (isAAPCS_ABI())
|
||||
stackAlignment = 8;
|
||||
|
||||
if (isTargetDarwin())
|
||||
if (!isTargetDarwin())
|
||||
UseMovt = hasV6T2Ops();
|
||||
else {
|
||||
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
|
||||
if (UseMOVT && hasV6T2Ops()) {
|
||||
unsigned Maj, Min, Rev;
|
||||
TargetTriple.getDarwinNumber(Maj, Min, Rev);
|
||||
UseMovt = (Maj > 4 || Min > 2);
|
||||
}
|
||||
}
|
||||
|
||||
if (!isThumb() || hasThumb2())
|
||||
PostRAScheduler = true;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc %s -mtriple=armv7-linux-gnueabi -arm-use-movt -filetype=obj -o - | \
|
||||
; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \
|
||||
; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s
|
||||
|
||||
target triple = "armv7-none-linux-gnueabi"
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc %s -mtriple=armv7-linux-gnueabi -arm-use-movt -relocation-model=pic -filetype=obj -o - | \
|
||||
; RUN: llc %s -mtriple=armv7-linux-gnueabi -relocation-model=pic -filetype=obj -o - | \
|
||||
; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=PIC01 %s
|
||||
|
||||
;; FIXME: Reduce this test further, or even better,
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc %s -mtriple=armv7-linux-gnueabi -arm-use-movt -filetype=obj -o - | \
|
||||
; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \
|
||||
; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s
|
||||
; RUN: llc %s -mtriple=armv7-linux-gnueabi -arm-use-movt -o - | \
|
||||
; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \
|
||||
; RUN: FileCheck -check-prefix=ASM %s
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user