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[Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumpr

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llvm-svn: 279241
This commit is contained in:
Krzysztof Parzyszek 2016-08-19 14:04:45 +00:00
parent 3cad3632a2
commit 53fcc0a9e4
5 changed files with 31 additions and 27 deletions
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19
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1292,8 +1292,27 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MI.setDesc(get(Hexagon::J2_jump));
return true;
case Hexagon::PS_tailcall_r:
case Hexagon::PS_jmpret:
MI.setDesc(get(Hexagon::J2_jumpr));
return true;
case Hexagon::PS_jmprett:
MI.setDesc(get(Hexagon::J2_jumprt));
return true;
case Hexagon::PS_jmpretf:
MI.setDesc(get(Hexagon::J2_jumprf));
return true;
case Hexagon::PS_jmprettnewpt:
MI.setDesc(get(Hexagon::J2_jumprtnewpt));
return true;
case Hexagon::PS_jmpretfnewpt:
MI.setDesc(get(Hexagon::J2_jumprfnewpt));
return true;
case Hexagon::PS_jmprettnew:
MI.setDesc(get(Hexagon::J2_jumprtnew));
return true;
case Hexagon::PS_jmpretfnew:
MI.setDesc(get(Hexagon::J2_jumprfnew));
return true;
}
return false;

2
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -1587,7 +1587,7 @@ let isTerminator = 1, hasSideEffects = 0 in {
defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
let isReturn = 1, isCodeGenOnly = 1 in
let isReturn = 1, isPseudo = 1, isCodeGenOnly = 1 in
defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel;
}

9
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
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@ -323,7 +323,6 @@ static bool doesModifyCalleeSavedReg(const MachineInstr &MI,
return false;
}
// TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
// Returns true if an instruction can be promoted to .new predicate or
// new-value store.
bool HexagonPacketizerList::isNewifiable(const MachineInstr &MI,
@ -333,7 +332,7 @@ bool HexagonPacketizerList::isNewifiable(const MachineInstr &MI,
if (NewRC == &Hexagon::PredRegsRegClass)
if (HII->isV60VectorInstruction(MI) && MI.mayStore())
return false;
return HII->isCondInst(MI) || MI.isReturn() || HII->mayBeNewStore(MI);
return HII->isCondInst(MI) || HII->isJumpR(MI) || HII->mayBeNewStore(MI);
}
// Promote an instructiont to its .cur form.
@ -798,10 +797,8 @@ bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
return false;
// predicate .new
// bug 5670: until that is fixed
// TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
if (RC == &Hexagon::PredRegsRegClass)
if (HII->isCondInst(MI) || MI.isReturn())
if (HII->isCondInst(MI) || HII->isJumpR(MI))
return HII->predCanBeUsedAsDotNew(PI, DepReg);
if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
@ -1291,7 +1288,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
RC = HRI->getMinimalPhysRegClass(DepReg);
}
if (I.isCall() || I.isReturn() || HII->isTailCall(I)) {
if (I.isCall() || HII->isJumpR(I) || HII->isTailCall(I)) {
if (!isRegDependence(DepType))
continue;
if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))

21
lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
View File

@ -262,25 +262,19 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
case Hexagon::PS_jmpret:
// jumpr r31
// Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
DstReg = MCI.getOperand(0).getReg();
if (Hexagon::R31 == DstReg) {
if (Hexagon::R31 == DstReg)
return HexagonII::HSIG_L2;
}
break;
case Hexagon::J2_jumprt:
case Hexagon::J2_jumprf:
case Hexagon::J2_jumprtnew:
case Hexagon::J2_jumprfnew:
case Hexagon::PS_jmprett:
case Hexagon::PS_jmpretf:
case Hexagon::PS_jmprettnew:
case Hexagon::PS_jmpretfnew:
case Hexagon::PS_jmprettnewpt:
case Hexagon::PS_jmpretfnewpt:
case Hexagon::J2_jumprtnewpt:
case Hexagon::J2_jumprfnewpt:
DstReg = MCI.getOperand(1).getReg();
SrcReg = MCI.getOperand(0).getReg();
// [if ([!]p0[.new])] jumpr r31
@ -811,25 +805,20 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
break; // none SUBInst deallocframe
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
case Hexagon::PS_jmpret:
Result.setOpcode(Hexagon::V4_SL2_jumpr31);
break; // none SUBInst jumpr r31
case Hexagon::J2_jumprf:
case Hexagon::PS_jmpretf:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_f);
break; // none SUBInst if (!p0) jumpr r31
case Hexagon::J2_jumprfnew:
case Hexagon::PS_jmpretfnewpt:
case Hexagon::PS_jmpretfnew:
case Hexagon::J2_jumprfnewpt:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_fnew);
break; // none SUBInst if (!p0.new) jumpr:nt r31
case Hexagon::J2_jumprt:
case Hexagon::PS_jmprett:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_t);
break; // none SUBInst if (p0) jumpr r31
case Hexagon::J2_jumprtnew:
case Hexagon::PS_jmprettnewpt:
case Hexagon::PS_jmprettnew:
case Hexagon::J2_jumprtnewpt:
Result.setOpcode(Hexagon::V4_SL2_jumpr31_tnew);
break; // none SUBInst if (p0.new) jumpr:nt r31
case Hexagon::L2_loadrb_io:

7
test/CodeGen/Hexagon/block-addr.ll
View File

@ -1,9 +1,8 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Allow combine(..##JTI..):
; CHECK: r{{[0-9]+}}{{.*}} = {{.*}}#.LJTI
; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
; CHECK: jumpr:nt r{{[0-9]+}}
; CHECK: .LJTI
; CHECK-DAG: r[[REG:[0-9]+]] = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
; CHECK-DAG: jumpr:nt r[[REG]]
define void @main() #0 {
entry: