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Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but
if it ever did it needs the def machinery. llvm-svn: 130549
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@ -137,6 +137,9 @@ class ARMFastISel : public FastISel {
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virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm);
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virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm1, uint64_t Imm2);
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virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, bool Op0IsKill,
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@ -434,6 +437,26 @@ unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm1, uint64_t Imm2) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addImm(Imm1).addImm(Imm2));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addImm(Imm1).addImm(Imm2));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY),
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ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, bool Op0IsKill,
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uint32_t Idx) {
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