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Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
64-bit vector shuffle. llvm-svn: 26964
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@ -202,7 +202,7 @@ public:
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/// support and the code generator is tasked with not creating illegal masks.
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bool isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const {
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return isOperationLegal(ISD::VECTOR_SHUFFLE, VT) &&
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isShuffleMaskLegal(Mask);
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isShuffleMaskLegal(Mask, VT);
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}
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/// getTypeToPromoteTo - If the action for this operation is to promote, this
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@ -489,7 +489,7 @@ protected:
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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virtual bool isShuffleMaskLegal(SDOperand Mask) const {
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virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
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return true;
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}
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@ -2371,7 +2371,10 @@ bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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bool X86TargetLowering::isShuffleMaskLegal(SDOperand Mask) const {
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bool
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X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
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// Only do shuffles on 128-bit vector types for now.
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if (MVT::getSizeInBits(VT) == 64) return false;
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return (X86::isSplatMask(Mask.Val) ||
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(Subtarget->hasSSE2() && X86::isPSHUFDMask(Mask.Val)));
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}
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@ -267,7 +267,7 @@ namespace llvm {
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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virtual bool isShuffleMaskLegal(SDOperand Mask) const;
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virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
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private:
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// C Calling Convention implementation.
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std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
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