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[X86][F16C] Regenerated f16c tests
llvm-svn: 279621
This commit is contained in:
Simon Pilgrim
parent
06e1775b78
commit
5441dbe832
@ -1,8 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefix=ALL --check-prefix=X32
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefix=ALL --check-prefix=X64
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; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefix=X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse3-builtins.c
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/f16c-builtins.c
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define float @test_cvtsh_ss(i16 %a0) nounwind {
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; X32-LABEL: test_cvtsh_ss:
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@ -1,10 +1,17 @@
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx,+f16c | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefix=X64
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define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_vcvtph2ps_128:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps
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; X32-LABEL: test_x86_vcvtph2ps_128:
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; X32: # BB#0:
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; X32-NEXT: vcvtph2ps %xmm0, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtph2ps_128:
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; X64: # BB#0:
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; X64-NEXT: vcvtph2ps %xmm0, %xmm0
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; X64-NEXT: retq
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%res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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@ -12,47 +19,79 @@ declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly
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define <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_vcvtph2ps_256:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps
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; X32-LABEL: test_x86_vcvtph2ps_256:
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; X32: # BB#0:
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; X32-NEXT: vcvtph2ps %xmm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtph2ps_256:
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; X64: # BB#0:
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; X64-NEXT: vcvtph2ps %xmm0, %ymm0
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; X64-NEXT: retq
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%res = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly
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define <8 x float> @test_x86_vcvtph2ps_256_m(<8 x i16>* nocapture %a) nounwind {
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entry:
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; CHECK-LABEL: test_x86_vcvtph2ps_256_m:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps (%
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%tmp1 = load <8 x i16>, <8 x i16>* %a, align 16
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%0 = tail call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %tmp1)
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ret <8 x float> %0
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; X32-LABEL: test_x86_vcvtph2ps_256_m:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vcvtph2ps (%eax), %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtph2ps_256_m:
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; X64: # BB#0:
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; X64-NEXT: vcvtph2ps (%rdi), %ymm0
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; X64-NEXT: retq
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%load = load <8 x i16>, <8 x i16>* %a, align 16
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%res = tail call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %load)
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ret <8 x float> %res
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}
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define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0) {
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; CHECK-LABEL: test_x86_vcvtps2ph_128:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph
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; X32-LABEL: test_x86_vcvtps2ph_128:
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; X32: # BB#0:
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; X32-NEXT: vcvtps2ph $0, %xmm0, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtps2ph_128:
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; X64: # BB#0:
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; X64-NEXT: vcvtps2ph $0, %xmm0, %xmm0
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; X64-NEXT: retq
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%res = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly
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define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) {
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; CHECK-LABEL: test_x86_vcvtps2ph_256:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph
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; X32-LABEL: test_x86_vcvtps2ph_256:
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; X32: # BB#0:
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; X32-NEXT: vcvtps2ph $0, %ymm0, %xmm0
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; X32-NEXT: vzeroupper
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtps2ph_256:
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; X64: # BB#0:
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; X64-NEXT: vcvtps2ph $0, %ymm0, %xmm0
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; X64-NEXT: vzeroupper
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; X64-NEXT: retq
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%res = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly
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define <4 x float> @test_x86_vcvtps2ph_128_scalar(i64* %ptr) {
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; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps (%
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; X32-LABEL: test_x86_vcvtps2ph_128_scalar:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vcvtph2ps (%eax), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtps2ph_128_scalar:
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; X64: # BB#0:
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; X64-NEXT: vcvtph2ps (%rdi), %xmm0
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; X64-NEXT: retq
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%load = load i64, i64* %ptr
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%ins1 = insertelement <2 x i64> undef, i64 %load, i32 0
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%ins2 = insertelement <2 x i64> %ins1, i64 0, i32 1
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@ -62,10 +101,16 @@ define <4 x float> @test_x86_vcvtps2ph_128_scalar(i64* %ptr) {
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}
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define <4 x float> @test_x86_vcvtps2ph_128_scalar2(i64* %ptr) {
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; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar2:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps (%
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; X32-LABEL: test_x86_vcvtps2ph_128_scalar2:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vcvtph2ps (%eax), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtps2ph_128_scalar2:
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; X64: # BB#0:
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; X64-NEXT: vcvtph2ps (%rdi), %xmm0
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; X64-NEXT: retq
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%load = load i64, i64* %ptr
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%ins = insertelement <2 x i64> undef, i64 %load, i32 0
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%bc = bitcast <2 x i64> %ins to <8 x i16>
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@ -74,20 +119,36 @@ define <4 x float> @test_x86_vcvtps2ph_128_scalar2(i64* %ptr) {
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}
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define void @test_x86_vcvtps2ph_256_m(<8 x i16>* nocapture %d, <8 x float> %a) nounwind {
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; X32-LABEL: test_x86_vcvtps2ph_256_m:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vcvtps2ph $3, %ymm0, (%eax)
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; X32-NEXT: vzeroupper
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtps2ph_256_m:
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; X64: # BB#0: # %entry
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; X64-NEXT: vcvtps2ph $3, %ymm0, (%rdi)
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; X64-NEXT: vzeroupper
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; X64-NEXT: retq
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entry:
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; CHECK-LABEL: test_x86_vcvtps2ph_256_m:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph $3, %ymm0, (%
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%0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a, i32 3)
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store <8 x i16> %0, <8 x i16>* %d, align 16
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ret void
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}
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define void @test_x86_vcvtps2ph_128_m(<4 x i16>* nocapture %d, <4 x float> %a) nounwind {
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; X32-LABEL: test_x86_vcvtps2ph_128_m:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vcvtps2ph $3, %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtps2ph_128_m:
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; X64: # BB#0: # %entry
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; X64-NEXT: vcvtps2ph $3, %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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; CHECK-LABEL: test_x86_vcvtps2ph_128_m:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph $3, %xmm0, (%
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%0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a, i32 3)
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%1 = shufflevector <8 x i16> %0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i16> %1, <4 x i16>* %d, align 8
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@ -95,10 +156,17 @@ entry:
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}
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define void @test_x86_vcvtps2ph_128_m2(double* nocapture %hf4x16, <4 x float> %f4x32) #0 {
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; X32-LABEL: test_x86_vcvtps2ph_128_m2:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vcvtps2ph $3, %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtps2ph_128_m2:
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; X64: # BB#0: # %entry
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; X64-NEXT: vcvtps2ph $3, %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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; CHECK-LABEL: test_x86_vcvtps2ph_128_m2:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph $3, %xmm0, (%
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%0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3)
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%1 = bitcast <8 x i16> %0 to <2 x double>
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%vecext = extractelement <2 x double> %1, i32 0
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@ -107,10 +175,17 @@ entry:
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}
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define void @test_x86_vcvtps2ph_128_m3(i64* nocapture %hf4x16, <4 x float> %f4x32) #0 {
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; X32-LABEL: test_x86_vcvtps2ph_128_m3:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vcvtps2ph $3, %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: test_x86_vcvtps2ph_128_m3:
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; X64: # BB#0: # %entry
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; X64-NEXT: vcvtps2ph $3, %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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; CHECK-LABEL: test_x86_vcvtps2ph_128_m3:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph $3, %xmm0, (%
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%0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3)
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%1 = bitcast <8 x i16> %0 to <2 x i64>
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%vecext = extractelement <2 x i64> %1, i32 0
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