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[X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions scheduler classes
llvm-svn: 319337
This commit is contained in:
Simon Pilgrim
parent
201c2b02d5
commit
5443a8a118
@ -8655,21 +8655,24 @@ multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
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// op(reg_vec2,mem_vec,imm)
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multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
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OpndItins itins, X86VectorVTInfo DestInfo,
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X86VectorVTInfo SrcInfo>{
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let ExeDomain = DestInfo.ExeDomain in {
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defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
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(ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
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OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
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(DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
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(SrcInfo.VT SrcInfo.RC:$src2),
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(i8 imm:$src3)))>;
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(i8 imm:$src3))), itins.rr>,
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Sched<[itins.Sched]>;
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defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
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(ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
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OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
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(DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
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(SrcInfo.VT (bitconvert
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(SrcInfo.LdFrag addr:$src2))),
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(i8 imm:$src3)))>;
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(i8 imm:$src3))), itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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@ -8677,8 +8680,8 @@ multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// op(reg_vec2,mem_vec,imm)
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// op(reg_vec2,broadcast(eltVt),imm)
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multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _>:
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avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
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OpndItins itins, X86VectorVTInfo _>:
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avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, itins, _, _>{
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let ExeDomain = _.ExeDomain in
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defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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@ -8687,7 +8690,8 @@ multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
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"$src1, ${src2}"##_.BroadcastStr##", $src3",
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(OpNode (_.VT _.RC:$src1),
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(_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
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(i8 imm:$src3))>, EVEX_B;
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(i8 imm:$src3)), itins.rm>, EVEX_B,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
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@ -8756,29 +8760,29 @@ multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
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}
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multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
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AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo,
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Predicate Pred = HasBWI> {
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OpndItins itins, AVX512VLVectorVTInfo DestInfo,
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AVX512VLVectorVTInfo SrcInfo, Predicate Pred = HasBWI> {
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let Predicates = [Pred] in {
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defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
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defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, itins, DestInfo.info512,
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SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
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}
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let Predicates = [Pred, HasVLX] in {
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defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
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defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, itins, DestInfo.info128,
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SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
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defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
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defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, itins, DestInfo.info256,
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SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
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}
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}
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multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
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bits<8> opc, SDNode OpNode,
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bits<8> opc, SDNode OpNode, OpndItins itins,
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Predicate Pred = HasAVX512> {
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let Predicates = [Pred] in {
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defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
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defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, itins, _.info512>, EVEX_V512;
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}
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let Predicates = [Pred, HasVLX] in {
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defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
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defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
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defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, itins, _.info128>, EVEX_V128;
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defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, itins, _.info256>, EVEX_V256;
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}
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}
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@ -8918,25 +8922,25 @@ def : Pat<(v4f64 (ftrunc VR256X:$src)),
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(VRNDSCALEPDZ256rri VR256X:$src, (i32 0xB))>;
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}
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multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
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bits<8> opc>{
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multiclass avx512_shuff_packed_128<string OpcodeStr, OpndItins itins,
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AVX512VLVectorVTInfo _, bits<8> opc>{
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let Predicates = [HasAVX512] in {
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defm Z : avx512_3Op_imm8<opc, OpcodeStr, X86Shuf128, _.info512>, EVEX_V512;
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defm Z : avx512_3Op_imm8<opc, OpcodeStr, X86Shuf128, itins, _.info512>, EVEX_V512;
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}
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let Predicates = [HasAVX512, HasVLX] in {
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defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, X86Shuf128, _.info256>, EVEX_V256;
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defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, X86Shuf128, itins, _.info256>, EVEX_V256;
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}
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}
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defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
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AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
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AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
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AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
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AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4", SSE_SHUFP,
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avx512vl_f32_info, 0x23>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2", SSE_SHUFP,
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avx512vl_f64_info, 0x23>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4", SSE_SHUFP,
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avx512vl_i32_info, 0x43>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2", SSE_SHUFP,
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avx512vl_i64_info, 0x43>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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let Predicates = [HasAVX512] in {
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// Provide fallback in case the load node that is used in the broadcast
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@ -8971,17 +8975,18 @@ def : Pat<(v64i8 (X86SubVBroadcast (v16i8 VR128X:$src))),
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0)>;
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}
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multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I> {
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defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
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multiclass avx512_valign<string OpcodeStr, OpndItins itins,
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AVX512VLVectorVTInfo VTInfo_I> {
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defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign, itins>,
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AVX512AIi8Base, EVEX_4V;
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}
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defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info>,
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defm VALIGND: avx512_valign<"valignd", SSE_PALIGN, avx512vl_i32_info>,
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EVEX_CD8<32, CD8VF>;
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defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info>,
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defm VALIGNQ: avx512_valign<"valignq", SSE_PALIGN, avx512vl_i64_info>,
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EVEX_CD8<64, CD8VF>, VEX_W;
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defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
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defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr", SSE_PALIGN,
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avx512vl_i8_info, avx512vl_i8_info>,
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EVEX_CD8<8, CD8VF>;
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@ -9103,7 +9108,8 @@ let Predicates = [HasVLX, HasBWI] in {
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}
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defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw",
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avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
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SSE_INTMUL_ITINS_P, avx512vl_i16_info, avx512vl_i8_info>,
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EVEX_CD8<8, CD8VF>;
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multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpndItins itins, X86VectorVTInfo _> {
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@ -9509,18 +9515,21 @@ defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
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extloadi16>, PD, VEX_WIG;
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defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
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defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
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//===----------------------------------------------------------------------===//
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// VSHUFPS - VSHUFPD Operations
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//===----------------------------------------------------------------------===//
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multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
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AVX512VLVectorVTInfo VTInfo_FP>{
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defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
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EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
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defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp,
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SSE_SHUFP>, EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
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AVX512AIi8Base, EVEX_4V;
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}
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defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
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defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
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//===----------------------------------------------------------------------===//
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// AVX-512 - Byte shift Left/Right
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//===----------------------------------------------------------------------===//
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@ -10101,26 +10110,27 @@ defm : vpclmulqdq_aliases<"VPCLMULQDQZ256", VR256X, i256mem>;
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//===----------------------------------------------------------------------===//
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multiclass VBMI2_shift_var_rm<bits<8> Op, string OpStr, SDNode OpNode,
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X86VectorVTInfo VTI> {
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OpndItins itins, X86VectorVTInfo VTI> {
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let Constraints = "$src1 = $dst",
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ExeDomain = VTI.ExeDomain in {
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defm r: AVX512_maskable_3src<Op, MRMSrcReg, VTI, (outs VTI.RC:$dst),
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(ins VTI.RC:$src2, VTI.RC:$src3), OpStr,
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"$src3, $src2", "$src2, $src3",
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(VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2, VTI.RC:$src3))>,
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AVX512FMA3Base;
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(VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2, VTI.RC:$src3)),
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itins.rr>, AVX512FMA3Base, Sched<[itins.Sched]>;
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defm m: AVX512_maskable_3src<Op, MRMSrcMem, VTI, (outs VTI.RC:$dst),
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(ins VTI.RC:$src2, VTI.MemOp:$src3), OpStr,
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"$src3, $src2", "$src2, $src3",
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(VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2,
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(VTI.VT (bitconvert (VTI.LdFrag addr:$src3)))))>,
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AVX512FMA3Base;
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(VTI.VT (bitconvert (VTI.LdFrag addr:$src3))))),
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itins.rm>, AVX512FMA3Base,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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multiclass VBMI2_shift_var_rmb<bits<8> Op, string OpStr, SDNode OpNode,
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X86VectorVTInfo VTI>
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: VBMI2_shift_var_rm<Op, OpStr, OpNode, VTI> {
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OpndItins itins, X86VectorVTInfo VTI>
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: VBMI2_shift_var_rm<Op, OpStr, OpNode, itins, VTI> {
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let Constraints = "$src1 = $dst",
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ExeDomain = VTI.ExeDomain in
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defm mb: AVX512_maskable_3src<Op, MRMSrcMem, VTI, (outs VTI.RC:$dst),
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@ -10128,54 +10138,57 @@ multiclass VBMI2_shift_var_rmb<bits<8> Op, string OpStr, SDNode OpNode,
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"${src3}"##VTI.BroadcastStr##", $src2",
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"$src2, ${src3}"##VTI.BroadcastStr,
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(OpNode VTI.RC:$src1, VTI.RC:$src2,
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(VTI.VT (X86VBroadcast (VTI.ScalarLdFrag addr:$src3))))>,
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AVX512FMA3Base, EVEX_B;
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(VTI.VT (X86VBroadcast (VTI.ScalarLdFrag addr:$src3)))),
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itins.rm>, AVX512FMA3Base, EVEX_B,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass VBMI2_shift_var_rm_common<bits<8> Op, string OpStr, SDNode OpNode,
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AVX512VLVectorVTInfo VTI> {
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OpndItins itins, AVX512VLVectorVTInfo VTI> {
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let Predicates = [HasVBMI2] in
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defm Z : VBMI2_shift_var_rm<Op, OpStr, OpNode, VTI.info512>, EVEX_V512;
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defm Z : VBMI2_shift_var_rm<Op, OpStr, OpNode, itins, VTI.info512>, EVEX_V512;
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let Predicates = [HasVBMI2, HasVLX] in {
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defm Z256 : VBMI2_shift_var_rm<Op, OpStr, OpNode, VTI.info256>, EVEX_V256;
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defm Z128 : VBMI2_shift_var_rm<Op, OpStr, OpNode, VTI.info128>, EVEX_V128;
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defm Z256 : VBMI2_shift_var_rm<Op, OpStr, OpNode, itins, VTI.info256>, EVEX_V256;
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defm Z128 : VBMI2_shift_var_rm<Op, OpStr, OpNode, itins, VTI.info128>, EVEX_V128;
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}
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}
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multiclass VBMI2_shift_var_rmb_common<bits<8> Op, string OpStr, SDNode OpNode,
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AVX512VLVectorVTInfo VTI> {
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OpndItins itins, AVX512VLVectorVTInfo VTI> {
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let Predicates = [HasVBMI2] in
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defm Z : VBMI2_shift_var_rmb<Op, OpStr, OpNode, VTI.info512>, EVEX_V512;
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defm Z : VBMI2_shift_var_rmb<Op, OpStr, OpNode, itins, VTI.info512>, EVEX_V512;
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let Predicates = [HasVBMI2, HasVLX] in {
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defm Z256 : VBMI2_shift_var_rmb<Op, OpStr, OpNode, VTI.info256>, EVEX_V256;
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defm Z128 : VBMI2_shift_var_rmb<Op, OpStr, OpNode, VTI.info128>, EVEX_V128;
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defm Z256 : VBMI2_shift_var_rmb<Op, OpStr, OpNode, itins, VTI.info256>, EVEX_V256;
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defm Z128 : VBMI2_shift_var_rmb<Op, OpStr, OpNode, itins, VTI.info128>, EVEX_V128;
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}
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}
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multiclass VBMI2_shift_var<bits<8> wOp, bits<8> dqOp, string Prefix,
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SDNode OpNode> {
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defm W : VBMI2_shift_var_rm_common<wOp, Prefix##"w", OpNode,
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SDNode OpNode, OpndItins itins> {
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defm W : VBMI2_shift_var_rm_common<wOp, Prefix##"w", OpNode, itins,
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avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
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defm D : VBMI2_shift_var_rmb_common<dqOp, Prefix##"d", OpNode,
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defm D : VBMI2_shift_var_rmb_common<dqOp, Prefix##"d", OpNode, itins,
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avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
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defm Q : VBMI2_shift_var_rmb_common<dqOp, Prefix##"q", OpNode,
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defm Q : VBMI2_shift_var_rmb_common<dqOp, Prefix##"q", OpNode, itins,
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avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
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}
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multiclass VBMI2_shift_imm<bits<8> wOp, bits<8> dqOp, string Prefix,
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SDNode OpNode> {
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defm W : avx512_common_3Op_rm_imm8<wOp, OpNode, Prefix##"w", avx512vl_i16_info,
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avx512vl_i16_info, HasVBMI2>, VEX_W, EVEX_CD8<16, CD8VF>;
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SDNode OpNode, OpndItins itins> {
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defm W : avx512_common_3Op_rm_imm8<wOp, OpNode, Prefix##"w", itins,
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avx512vl_i16_info, avx512vl_i16_info, HasVBMI2>,
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VEX_W, EVEX_CD8<16, CD8VF>;
|
||||
defm D : avx512_common_3Op_imm8<Prefix##"d", avx512vl_i32_info, dqOp,
|
||||
OpNode, HasVBMI2>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
|
||||
OpNode, itins, HasVBMI2>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
|
||||
defm Q : avx512_common_3Op_imm8<Prefix##"q", avx512vl_i64_info, dqOp, OpNode,
|
||||
HasVBMI2>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
|
||||
itins, HasVBMI2>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
|
||||
}
|
||||
|
||||
// Concat & Shift
|
||||
defm VPSHLDV : VBMI2_shift_var<0x70, 0x71, "vpshldv", X86VShldv>;
|
||||
defm VPSHRDV : VBMI2_shift_var<0x72, 0x73, "vpshrdv", X86VShrdv>;
|
||||
defm VPSHLD : VBMI2_shift_imm<0x70, 0x71, "vpshld", X86VShld>;
|
||||
defm VPSHRD : VBMI2_shift_imm<0x72, 0x73, "vpshrd", X86VShrd>;
|
||||
defm VPSHLDV : VBMI2_shift_var<0x70, 0x71, "vpshldv", X86VShldv, SSE_INTMUL_ITINS_P>;
|
||||
defm VPSHRDV : VBMI2_shift_var<0x72, 0x73, "vpshrdv", X86VShrdv, SSE_INTMUL_ITINS_P>;
|
||||
defm VPSHLD : VBMI2_shift_imm<0x70, 0x71, "vpshld", X86VShld, SSE_INTMUL_ITINS_P>;
|
||||
defm VPSHRD : VBMI2_shift_imm<0x72, 0x73, "vpshrd", X86VShrd, SSE_INTMUL_ITINS_P>;
|
||||
|
||||
// Compress
|
||||
defm VPCOMPRESSB : compress_by_elt_width <0x63, "vpcompressb", avx512vl_i8_info,
|
||||
HasVBMI2>, EVEX;
|
||||
@ -10290,9 +10303,9 @@ defm GF2P8MULB : GF2P8MULB_avx512_common<0xCF, "vgf2p8mulb", X86GF2P8mulb>,
|
||||
EVEX_CD8<8, CD8VF>, T8PD;
|
||||
|
||||
multiclass GF2P8AFFINE_avx512_rmb_imm<bits<8> Op, string OpStr, SDNode OpNode,
|
||||
X86VectorVTInfo VTI,
|
||||
OpndItins itins, X86VectorVTInfo VTI,
|
||||
X86VectorVTInfo BcstVTI>
|
||||
: avx512_3Op_rm_imm8<Op, OpStr, OpNode, VTI, VTI> {
|
||||
: avx512_3Op_rm_imm8<Op, OpStr, OpNode, itins, VTI, VTI> {
|
||||
let ExeDomain = VTI.ExeDomain in
|
||||
defm rmbi : AVX512_maskable<Op, MRMSrcMem, VTI, (outs VTI.RC:$dst),
|
||||
(ins VTI.RC:$src1, VTI.ScalarMemOp:$src2, u8imm:$src3),
|
||||
@ -10300,25 +10313,27 @@ multiclass GF2P8AFFINE_avx512_rmb_imm<bits<8> Op, string OpStr, SDNode OpNode,
|
||||
"$src1, ${src2}"##BcstVTI.BroadcastStr##", $src3",
|
||||
(OpNode (VTI.VT VTI.RC:$src1),
|
||||
(bitconvert (BcstVTI.VT (X86VBroadcast (loadi64 addr:$src2)))),
|
||||
(i8 imm:$src3))>, EVEX_B;
|
||||
(i8 imm:$src3)), itins.rm>, EVEX_B,
|
||||
Sched<[itins.Sched.Folded, ReadAfterLd]>;
|
||||
}
|
||||
|
||||
multiclass GF2P8AFFINE_avx512_common<bits<8> Op, string OpStr, SDNode OpNode> {
|
||||
multiclass GF2P8AFFINE_avx512_common<bits<8> Op, string OpStr, SDNode OpNode,
|
||||
OpndItins itins> {
|
||||
let Predicates = [HasGFNI, HasAVX512, HasBWI] in
|
||||
defm Z : GF2P8AFFINE_avx512_rmb_imm<Op, OpStr, OpNode, v64i8_info,
|
||||
defm Z : GF2P8AFFINE_avx512_rmb_imm<Op, OpStr, OpNode, itins, v64i8_info,
|
||||
v8i64_info>, EVEX_V512;
|
||||
let Predicates = [HasGFNI, HasVLX, HasBWI] in {
|
||||
defm Z256 : GF2P8AFFINE_avx512_rmb_imm<Op, OpStr, OpNode, v32i8x_info,
|
||||
defm Z256 : GF2P8AFFINE_avx512_rmb_imm<Op, OpStr, OpNode, itins, v32i8x_info,
|
||||
v4i64x_info>, EVEX_V256;
|
||||
defm Z128 : GF2P8AFFINE_avx512_rmb_imm<Op, OpStr, OpNode, v16i8x_info,
|
||||
defm Z128 : GF2P8AFFINE_avx512_rmb_imm<Op, OpStr, OpNode, itins, v16i8x_info,
|
||||
v2i64x_info>, EVEX_V128;
|
||||
}
|
||||
}
|
||||
|
||||
defm GF2P8AFFINEINVQB : GF2P8AFFINE_avx512_common<0xCF, "vgf2p8affineinvqb",
|
||||
X86GF2P8affineinvqb>,
|
||||
X86GF2P8affineinvqb, SSE_INTMUL_ITINS_P>,
|
||||
EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base;
|
||||
defm GF2P8AFFINEQB : GF2P8AFFINE_avx512_common<0xCE, "vgf2p8affineqb",
|
||||
X86GF2P8affineqb>,
|
||||
X86GF2P8affineqb, SSE_INTMUL_ITINS_P>,
|
||||
EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base;
|
||||
|
||||
|
||||
@ -7331,7 +7331,7 @@ define <64 x i8> @vmov_test16(i64 %x) {
|
||||
; GENERIC-NEXT: movl $32, %eax # sched: [1:0.33]
|
||||
; GENERIC-NEXT: kmovd %eax, %k1
|
||||
; GENERIC-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1}
|
||||
; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]
|
||||
; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7] sched: [1:1.00]
|
||||
; GENERIC-NEXT: vpmovb2m %zmm0, %k0
|
||||
; GENERIC-NEXT: vpmovm2b %k0, %zmm0
|
||||
; GENERIC-NEXT: retq # sched: [1:1.00]
|
||||
@ -7371,7 +7371,7 @@ define <64 x i8> @vmov_test17(i64 %x, i32 %y, i32 %z) {
|
||||
; GENERIC-NEXT: movl $32, %eax # sched: [1:0.33]
|
||||
; GENERIC-NEXT: kmovd %eax, %k1
|
||||
; GENERIC-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1}
|
||||
; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7]
|
||||
; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7] sched: [1:1.00]
|
||||
; GENERIC-NEXT: vpmovb2m %zmm0, %k0
|
||||
; GENERIC-NEXT: vpmovm2b %k0, %zmm0
|
||||
; GENERIC-NEXT: retq # sched: [1:1.00]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user