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R600/SI: Get rid of FCLAMP_SI pseudo

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It's not necessary. Also use complex patterns to allow
src modifier usage.

llvm-svn: 221916
This commit is contained in:
Matt Arsenault 2014-11-13 19:49:04 +00:00
parent 8e7c697444
commit 5487619f0a
5 changed files with 54 additions and 25 deletions
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12
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
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@ -111,6 +111,9 @@ private:
bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
SDValue &Clamp, SDValue &Omod) const;
bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
SDValue &Omod) const;
SDNode *SelectADD_SUB_I64(SDNode *N);
SDNode *SelectDIV_SCALE(SDNode *N);
@ -1129,6 +1132,15 @@ bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
return SelectVOP3Mods(In, Src, SrcMods);
}
bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
SDValue &SrcMods,
SDValue &Omod) const {
// FIXME: Handle Omod
Omod = CurDAG->getTargetConstant(0, MVT::i32);
return SelectVOP3Mods(In, Src, SrcMods);
}
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
const AMDGPUTargetLowering& Lowering =
*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());

14
lib/Target/R600/SIISelLowering.cpp
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@ -635,20 +635,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
}
case AMDGPU::FCLAMP_SI: {
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
getTargetMachine().getSubtargetImpl()->getInstrInfo());
DebugLoc DL = MI->getDebugLoc();
unsigned DestReg = MI->getOperand(0).getReg();
BuildMI(*BB, I, DL, TII->get(AMDGPU::V_ADD_F32_e64), DestReg)
.addImm(0) // SRC0 modifiers
.addOperand(MI->getOperand(1))
.addImm(0) // SRC1 modifiers
.addImm(0) // SRC1
.addImm(1) // CLAMP
.addImm(0); // OMOD
MI->eraseFromParent();
}
}
return BB;
}

1
lib/Target/R600/SIInstrInfo.td
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@ -245,6 +245,7 @@ def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
//===----------------------------------------------------------------------===//

14
lib/Target/R600/SIInstructions.td
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@ -2387,18 +2387,10 @@ def : BitConvert <v16f32, v16i32, VReg_512>;
/********** Src & Dst modifiers **********/
/********** =================== **********/
def FCLAMP_SI : AMDGPUShaderInst <
(outs VReg_32:$dst),
(ins VSrc_32:$src0),
"fclamp_si $dst, $src0",
[]
> {
let usesCustomInserter = 1;
}
def : Pat <
(AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
(FCLAMP_SI f32:$src)
(AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod),
(f32 FP_ZERO), (f32 FP_ONE)),
(V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod)
>;
/********** ================================ **********/

38
test/CodeGen/R600/llvm.AMDGPU.clamp.ll
View File

@ -1,6 +1,7 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
declare float @llvm.fabs.f32(float) nounwind readnone
declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone
declare float @llvm.AMDIL.clamp.f32(float, float, float) nounwind readnone
@ -17,6 +18,43 @@ define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
ret void
}
; FUNC-LABEL: {{^}}clamp_fabs_0_1_f32:
; SI: s_load_dword [[ARG:s[0-9]+]],
; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, |[[ARG]]| clamp{{$}}
; SI: buffer_store_dword [[RESULT]]
; SI: s_endpgm
define void @clamp_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
%src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fabs, float 0.0, float 1.0) nounwind readnone
store float %clamp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}clamp_fneg_0_1_f32:
; SI: s_load_dword [[ARG:s[0-9]+]],
; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -[[ARG]] clamp{{$}}
; SI: buffer_store_dword [[RESULT]]
; SI: s_endpgm
define void @clamp_fneg_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
%src.fneg = fsub float -0.0, %src
%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg, float 0.0, float 1.0) nounwind readnone
store float %clamp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}clamp_fneg_fabs_0_1_f32:
; SI: s_load_dword [[ARG:s[0-9]+]],
; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -|[[ARG]]| clamp{{$}}
; SI: buffer_store_dword [[RESULT]]
; SI: s_endpgm
define void @clamp_fneg_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
%src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
%src.fneg.fabs = fsub float -0.0, %src.fabs
%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg.fabs, float 0.0, float 1.0) nounwind readnone
store float %clamp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}clamp_0_1_amdil_legacy_f32:
; SI: s_load_dword [[ARG:s[0-9]+]],
; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}