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[ARM] MVE and scalar postinc mir tests. NFC
This commit is contained in:
David Green
parent
ca88e6d173
commit
54b3bad454
889
test/CodeGen/Thumb2/mve-postinc-distribute.mir
Normal file
889
test/CodeGen/Thumb2/mve-postinc-distribute.mir
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@ -0,0 +1,889 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s
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--- |
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define i32* @MVE_VLDRWU32(i32* %x) { unreachable }
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define i32* @MVE_VLDRHU16(i32* %x) { unreachable }
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define i32* @MVE_VLDRBU8(i32* %x) { unreachable }
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define i32* @MVE_VLDRBS32(i32* %x) { unreachable }
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define i32* @MVE_VLDRBU32(i32* %x) { unreachable }
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define i32* @MVE_VLDRHS32(i32* %x) { unreachable }
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define i32* @MVE_VLDRHU32(i32* %x) { unreachable }
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define i32* @MVE_VLDRBS16(i32* %x) { unreachable }
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define i32* @MVE_VLDRBU16(i32* %x) { unreachable }
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define i32* @MVE_VSTRWU32(i32* %x, <4 x i32> %y) { unreachable }
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define i32* @MVE_VSTRHU16(i32* %x, <4 x i32> %y) { unreachable }
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define i32* @MVE_VSTRBU8(i32* %x, <4 x i32> %y) { unreachable }
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define i32* @MVE_VSTRH32(i32* %x, <4 x i32> %y) { unreachable }
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define i32* @MVE_VSTRB32(i32* %x, <4 x i32> %y) { unreachable }
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define i32* @MVE_VSTRB16(i32* %x, <4 x i32> %y) { unreachable }
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define i32* @ld0ld4(i32* %x) { unreachable }
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define i32* @ld4ld0(i32* %x) { unreachable }
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define i32* @ld0ld4ld0(i32* %x) { unreachable }
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define i32* @ld4ld0ld4(i32* %x) { unreachable }
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define i32* @addload(i32* %x) { unreachable }
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define i32* @sub(i32* %x) { unreachable }
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define i32* @otherUse(i32* %x) { unreachable }
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define i32* @postincUse(i32* %x) { unreachable }
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define i32* @badScale(i32* %x) { unreachable }
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define i32* @badRange(i32* %x) { unreachable }
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define i32* @addUseOK(i32* %x) { unreachable }
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define i32* @addUseDom(i32* %x) { unreachable }
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define i32* @addUseKilled(i32* %x) { unreachable }
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...
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---
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name: MVE_VLDRWU32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRWU32
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:gprnopc = COPY $r0
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%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VLDRHU16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRHU16
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:gprnopc = COPY $r0
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%1:mqpr = MVE_VLDRHU16 %0, 0, 0, $noreg :: (load 16, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VLDRBU8
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRBU8
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:gprnopc = COPY $r0
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%1:mqpr = MVE_VLDRBU8 %0, 0, 0, $noreg :: (load 16, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VLDRBS32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: tgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRBS32
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[COPY]], 0, 0, $noreg :: (load 4, align 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:tgpr = COPY $r0
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%1:mqpr = MVE_VLDRBS32 %0, 0, 0, $noreg :: (load 4, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VLDRBU32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: tgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRBU32
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[COPY]], 0, 0, $noreg :: (load 4, align 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:tgpr = COPY $r0
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%1:mqpr = MVE_VLDRBU32 %0, 0, 0, $noreg :: (load 4, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VLDRHS32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: tgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRHS32
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[COPY]], 0, 0, $noreg :: (load 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:tgpr = COPY $r0
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%1:mqpr = MVE_VLDRHS32 %0, 0, 0, $noreg :: (load 8, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VLDRHU32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: tgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRHU32
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[COPY]], 0, 0, $noreg :: (load 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:tgpr = COPY $r0
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%1:mqpr = MVE_VLDRHU32 %0, 0, 0, $noreg :: (load 8, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VLDRBS16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: tgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRBS16
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[COPY]], 0, 0, $noreg :: (load 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:tgpr = COPY $r0
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%1:mqpr = MVE_VLDRBS16 %0, 0, 0, $noreg :: (load 8, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VLDRBU16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: tgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VLDRBU16
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[COPY]], 0, 0, $noreg :: (load 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:tgpr = COPY $r0
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%1:mqpr = MVE_VLDRBU16 %0, 0, 0, $noreg :: (load 8, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VSTRWU32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VSTRWU32
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: MVE_VSTRWU32 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 16, align 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%1:mqpr = COPY $q0
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%0:gprnopc = COPY $r0
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MVE_VSTRWU32 %1, %0, 0, 0, $noreg :: (store 16, align 8)
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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...
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---
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name: MVE_VSTRHU16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$q0', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $r0, $q0
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; CHECK-LABEL: name: MVE_VSTRHU16
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: MVE_VSTRHU16 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 16, align 8)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%1:mqpr = COPY $q0
|
||||
%0:gprnopc = COPY $r0
|
||||
MVE_VSTRHU16 %1, %0, 0, 0, $noreg :: (store 16, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: MVE_VSTRBU8
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: MVE_VSTRBU8
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: MVE_VSTRBU8 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 16, align 8)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%1:mqpr = COPY $q0
|
||||
%0:gprnopc = COPY $r0
|
||||
MVE_VSTRBU8 %1, %0, 0, 0, $noreg :: (store 16, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: MVE_VSTRH32
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: tgpr, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: MVE_VSTRH32
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
|
||||
; CHECK: MVE_VSTRH32 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 8)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%1:mqpr = COPY $q0
|
||||
%0:tgpr = COPY $r0
|
||||
MVE_VSTRH32 %1, %0, 0, 0, $noreg :: (store 8, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: MVE_VSTRB32
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: tgpr, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: MVE_VSTRB32
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
|
||||
; CHECK: MVE_VSTRB32 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 4, align 8)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%1:mqpr = COPY $q0
|
||||
%0:tgpr = COPY $r0
|
||||
MVE_VSTRB32 %1, %0, 0, 0, $noreg :: (store 4, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: MVE_VSTRB16
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: tgpr, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: MVE_VSTRB16
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
|
||||
; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 8)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%1:mqpr = COPY $q0
|
||||
%0:tgpr = COPY $r0
|
||||
MVE_VSTRB16 %1, %0, 0, 0, $noreg :: (store 8, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: ld0ld4
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: ld0ld4
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: ld4ld0
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: ld4ld0
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: ld0ld4ld0
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
- { id: 4, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: ld0ld4ld0
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[MVE_VLDRWU32_2:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
%4:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: ld4ld0ld4
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
- { id: 4, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: ld4ld0ld4
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[MVE_VLDRWU32_2:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%4:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: addload
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: addload
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: sub
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: sub
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2SUBri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: otherUse
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: otherUse
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[COPY]]
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %0
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: postincUse
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
- { id: 4, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: postincUse
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: badScale
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: badScale
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 3, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2SUBri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2SUBri %0, 3, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: badRange
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: badRange
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], -300, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], -300, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2SUBri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2SUBri %0, -300, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, -300, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: addUseOK
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
- { id: 4, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: addUseOK
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2LSRri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
%4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg
|
||||
$r0 = COPY %4
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: addUseDom
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
- { id: 4, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: addUseDom
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2LSRri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
|
||||
%4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %4
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: addUseKilled
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: mqpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
- { id: 3, class: mqpr, preferred-register: '' }
|
||||
- { id: 4, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$q0', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $q0
|
||||
|
||||
; CHECK-LABEL: name: addUseKilled
|
||||
; CHECK: liveins: $r0, $q0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri killed [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
|
||||
; CHECK: $r0 = COPY [[t2LSRri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
|
||||
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
|
||||
%4:rgpr = nuw t2LSRri killed %2, 2, 14, $noreg, $noreg
|
||||
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
|
||||
$r0 = COPY %4
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
267
test/CodeGen/Thumb2/postinc-distribute.mir
Normal file
267
test/CodeGen/Thumb2/postinc-distribute.mir
Normal file
@ -0,0 +1,267 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
define i32* @t2LDRi12(i32* %x, i32 %y) { unreachable }
|
||||
define i32* @t2LDRHi12(i32* %x, i32 %y) { unreachable }
|
||||
define i32* @t2LDRSHi12(i32* %x, i32 %y) { unreachable }
|
||||
define i32* @t2LDRBi12(i32* %x, i32 %y) { unreachable }
|
||||
define i32* @t2LDRSBi12(i32* %x, i32 %y) { unreachable }
|
||||
define i32* @t2STRi12(i32* %x, i32 %y) { unreachable }
|
||||
define i32* @t2STRHi12(i32* %x, i32 %y) { unreachable }
|
||||
define i32* @t2STRBi12(i32* %x, i32 %y) { unreachable }
|
||||
|
||||
define i32* @storedadd(i32* %x, i32 %y) { unreachable }
|
||||
|
||||
...
|
||||
---
|
||||
name: t2LDRi12
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0
|
||||
|
||||
; CHECK-LABEL: name: t2LDRi12
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2LDRi12_:%[0-9]+]]:rgpr = t2LDRi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 4)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = t2LDRi12 %0, 0, 14, $noreg :: (load 4, align 4)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: t2LDRHi12
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0
|
||||
|
||||
; CHECK-LABEL: name: t2LDRHi12
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2LDRHi12_:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 4)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = t2LDRHi12 %0, 0, 14, $noreg :: (load 4, align 4)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: t2LDRSHi12
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0
|
||||
|
||||
; CHECK-LABEL: name: t2LDRSHi12
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2LDRSHi12_:%[0-9]+]]:rgpr = t2LDRSHi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 4)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = t2LDRSHi12 %0, 0, 14, $noreg :: (load 4, align 4)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: t2LDRBi12
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0
|
||||
|
||||
; CHECK-LABEL: name: t2LDRBi12
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 4)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load 4, align 4)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: t2LDRSBi12
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0
|
||||
|
||||
; CHECK-LABEL: name: t2LDRSBi12
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2LDRSBi12_:%[0-9]+]]:rgpr = t2LDRSBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load 4)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = t2LDRSBi12 %0, 0, 14, $noreg :: (load 4, align 4)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: t2STRi12
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$r1', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $r1
|
||||
|
||||
; CHECK-LABEL: name: t2STRi12
|
||||
; CHECK: liveins: $r0, $r1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
|
||||
; CHECK: t2STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 4)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = COPY $r1
|
||||
t2STRi12 %1:rgpr, %0, 0, 14, $noreg :: (store 4, align 4)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: t2STRHi12
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$r1', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $r1
|
||||
|
||||
; CHECK-LABEL: name: t2STRHi12
|
||||
; CHECK: liveins: $r0, $r1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
|
||||
; CHECK: t2STRHi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 4)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = COPY $r1
|
||||
t2STRHi12 %1:rgpr, %0, 0, 14, $noreg :: (store 4, align 4)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: t2STRBi12
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
- { id: 2, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
- { reg: '$r1', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0, $r1
|
||||
|
||||
; CHECK-LABEL: name: t2STRBi12
|
||||
; CHECK: liveins: $r0, $r1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
|
||||
; CHECK: t2STRBi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 4)
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = COPY $r1
|
||||
t2STRBi12 %1:rgpr, %0, 0, 14, $noreg :: (store 4, align 4)
|
||||
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
$r0 = COPY %2
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
---
|
||||
name: storedadd
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprnopc, preferred-register: '' }
|
||||
- { id: 1, class: rgpr, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0
|
||||
|
||||
; CHECK-LABEL: name: storedadd
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
|
||||
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
|
||||
; CHECK: t2STRi12 [[t2ADDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 4)
|
||||
; CHECK: $r0 = COPY [[t2ADDri]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||||
%0:gprnopc = COPY $r0
|
||||
%1:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
|
||||
t2STRi12 %1, %0, 0, 14, $noreg :: (store 4, align 4)
|
||||
$r0 = COPY %1
|
||||
tBX_RET 14, $noreg, implicit $r0
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user