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Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
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@ -110,6 +110,11 @@ def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
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def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
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"Is microcontroller profile ('M' series)">;
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"Is microcontroller profile ('M' series)">;
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// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
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// See ARMInstrInfo.td for details.
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def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
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"NaCl trap">;
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// ARM ISAs.
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// ARM ISAs.
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def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
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def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
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"Support ARM v4T instructions">;
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"Support ARM v4T instructions">;
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@ -1693,6 +1693,13 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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}
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}
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break;
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break;
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}
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}
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case ARM::TRAPNaCl: {
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//.long 0xe7fedef0 @ trap
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uint32_t Val = 0xe7fedef0UL;
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OutStreamer.AddComment("trap");
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OutStreamer.EmitIntValue(Val, 4);
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return;
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}
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case ARM::tTRAP: {
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case ARM::tTRAP: {
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// Non-Darwin binutils don't yet support the "trap" mnemonic.
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// Non-Darwin binutils don't yet support the "trap" mnemonic.
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// FIXME: Remove this special case when they do.
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// FIXME: Remove this special case when they do.
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@ -2562,7 +2562,8 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
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return SelectCall(&I, "memset");
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return SelectCall(&I, "memset");
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}
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}
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case Intrinsic::trap: {
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case Intrinsic::trap: {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::TRAP));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(
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Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
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return true;
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return true;
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}
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}
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}
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}
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@ -6303,7 +6303,16 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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DispatchBB->setIsLandingPad();
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DispatchBB->setIsLandingPad();
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MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
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MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
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BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
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unsigned trap_opcode;
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if (Subtarget->isThumb()) {
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trap_opcode = ARM::tTRAP;
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} else {
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if (Subtarget->useNaClTrap())
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trap_opcode = ARM::TRAPNaCl;
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else
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trap_opcode = ARM::TRAP;
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}
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BuildMI(TrapBB, dl, TII->get(trap_opcode));
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DispatchBB->addSuccessor(TrapBB);
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DispatchBB->addSuccessor(TrapBB);
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MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
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MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
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@ -10317,4 +10326,3 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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return false;
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return false;
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}
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}
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@ -239,6 +239,9 @@ def IsARM : Predicate<"!Subtarget->isThumb()">,
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def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
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def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
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def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
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def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
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def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
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def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
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def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
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AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
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def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
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// FIXME: Eventually this will be just "hasV6T2Ops".
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// FIXME: Eventually this will be just "hasV6T2Ops".
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def UseMovt : Predicate<"Subtarget->useMovt()">;
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def UseMovt : Predicate<"Subtarget->useMovt()">;
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@ -1762,11 +1765,32 @@ def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
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let Inst{3-0} = opt;
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let Inst{3-0} = opt;
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}
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}
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// A5.4 Permanently UNDEFINED instructions.
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/*
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* A5.4 Permanently UNDEFINED instructions.
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*
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* For most targets use UDF #65006, for which the OS will generate SIGTRAP.
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* Other UDF encodings generate SIGILL.
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*
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* NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
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* Encoding A1:
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* 1110 0111 1111 iiii iiii iiii 1111 iiii
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* Encoding T1:
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* 1101 1110 iiii iiii
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* It uses the following encoding:
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* 1110 0111 1111 1110 1101 1110 1111 0000
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* - In ARM: UDF #60896;
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* - In Thumb: UDF #254 followed by a branch-to-self.
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*/
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let isBarrier = 1, isTerminator = 1 in
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def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
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"trap", [(trap)]>,
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Requires<[IsARM,UseNaClTrap]> {
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let Inst = 0xe7fedef0;
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}
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let isBarrier = 1, isTerminator = 1 in
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let isBarrier = 1, isTerminator = 1 in
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def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
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def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
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"trap", [(trap)]>,
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"trap", [(trap)]>,
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Requires<[IsARM]> {
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Requires<[IsARM,DontUseNaClTrap]> {
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let Inst = 0xe7ffdefe;
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let Inst = 0xe7ffdefe;
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}
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}
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@ -80,6 +80,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
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, FPOnlySP(false)
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, FPOnlySP(false)
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, AllowsUnalignedMem(false)
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, AllowsUnalignedMem(false)
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, Thumb2DSP(false)
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, Thumb2DSP(false)
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, UseNaClTrap(false)
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, stackAlignment(4)
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, stackAlignment(4)
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, CPUString(CPU)
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, CPUString(CPU)
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, TargetTriple(TT)
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, TargetTriple(TT)
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@ -156,6 +156,9 @@ protected:
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/// and such) instructions in Thumb2 code.
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/// and such) instructions in Thumb2 code.
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bool Thumb2DSP;
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bool Thumb2DSP;
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/// NaCl TRAP instruction is generated instead of the regular TRAP.
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bool UseNaClTrap;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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/// entry to the function and which must be maintained by every function.
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unsigned stackAlignment;
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unsigned stackAlignment;
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@ -241,6 +244,7 @@ protected:
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bool hasRAS() const { return HasRAS; }
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bool hasRAS() const { return HasRAS; }
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bool hasMPExtension() const { return HasMPExtension; }
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bool hasMPExtension() const { return HasMPExtension; }
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bool hasThumb2DSP() const { return Thumb2DSP; }
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bool hasThumb2DSP() const { return Thumb2DSP; }
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bool useNaClTrap() const { return UseNaClTrap; }
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bool hasFP16() const { return HasFP16; }
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bool hasFP16() const { return HasFP16; }
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bool hasD16() const { return HasD16; }
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bool hasD16() const { return HasD16; }
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@ -11,11 +11,12 @@
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "ARMMCTargetDesc.h"
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#include "ARMBaseInfo.h"
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#include "ARMBaseInfo.h"
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#include "ARMELFStreamer.h"
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#include "ARMELFStreamer.h"
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#include "ARMMCAsmInfo.h"
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#include "ARMMCAsmInfo.h"
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#include "ARMMCTargetDesc.h"
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#include "InstPrinter/ARMInstPrinter.h"
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#include "InstPrinter/ARMInstPrinter.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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@ -37,6 +38,8 @@
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using namespace llvm;
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using namespace llvm;
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std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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Triple triple(TT);
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// Set the boolean corresponding to the current target triple, or the default
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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// if one cannot be determined, to true.
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unsigned Len = TT.size();
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unsigned Len = TT.size();
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@ -119,6 +122,13 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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ARMArchFeature += ",+thumb-mode";
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ARMArchFeature += ",+thumb-mode";
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}
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}
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if (triple.isOSNaCl()) {
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if (ARMArchFeature.empty())
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ARMArchFeature = "+nacl-trap";
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else
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ARMArchFeature += ",+nacl-trap";
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}
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return ARMArchFeature;
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return ARMArchFeature;
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}
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}
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@ -1,5 +1,23 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=INSTR
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; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=INSTR
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; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap | FileCheck %s -check-prefix=FUNC
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; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap | FileCheck %s -check-prefix=FUNC
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; RUN: llc -mtriple=armv7-unknown-nacl -filetype=obj %s -o - \
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; RUN: | llvm-objdump -disassemble -triple armv7-unknown-nacl - \
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; RUN: | FileCheck %s -check-prefix=ENCODING-NACL
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; RUN: llc -mtriple=armv7-unknown-nacl -filetype=obj %s -o - \
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; RUN: | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \
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; RUN: | FileCheck %s -check-prefix=ENCODING-NACL
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; RUN: llc -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \
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; RUN: | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \
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; RUN: | FileCheck %s -check-prefix=ENCODING-NACL
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; RUN: llc -fast-isel -mtriple=armv7-unknown-nacl -filetype=obj %s -o - \
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; RUN: | llvm-objdump -disassemble -triple armv7-unknown-nacl - \
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; RUN: | FileCheck %s -check-prefix=ENCODING-NACL
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; RUN: llc -mtriple=armv7 -filetype=obj %s -o - \
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; RUN: | llvm-objdump -disassemble -triple armv7 - \
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; RUN: | FileCheck %s -check-prefix=ENCODING-ALL
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; RUN: llc -fast-isel -mtriple=armv7 -filetype=obj %s -o - \
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; RUN: | llvm-objdump -disassemble -triple armv7 - \
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; RUN: | FileCheck %s -check-prefix=ENCODING-ALL
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; rdar://7961298
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; rdar://7961298
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; rdar://9249183
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; rdar://9249183
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@ -10,6 +28,11 @@ entry:
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; FUNC: t:
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; FUNC: t:
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; FUNC: bl __trap
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; FUNC: bl __trap
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; ENCODING-NACL: f0 de fe e7
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; ENCODING-ALL: fe de ff e7
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call void @llvm.trap()
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call void @llvm.trap()
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unreachable
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unreachable
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}
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}
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@ -21,6 +44,11 @@ entry:
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; FUNC: t2:
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; FUNC: t2:
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; FUNC: bl __trap
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; FUNC: bl __trap
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; ENCODING-NACL: f0 de fe e7
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; ENCODING-ALL: fe de ff e7
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call void @llvm.debugtrap()
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call void @llvm.debugtrap()
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unreachable
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unreachable
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}
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}
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@ -1,7 +1,14 @@
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@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
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@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s \
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@ RUN: | FileCheck %s -check-prefix=ALL
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@ RUN: llvm-mc -mcpu=cortex-a9-mp -triple armv7-unknown-nacl -show-encoding %s \
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@ RUN: | FileCheck %s -check-prefix=NACL
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@ RUN: llvm-mc -mcpu=cortex-a8 -mattr=+nacl-trap -triple armv7 -show-encoding %s \
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@ RUN: | FileCheck %s -check-prefix=NACL
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@ CHECK: trap
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@ ALL: trap
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@ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
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@ ALL: encoding: [0xfe,0xde,0xff,0xe7]
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@ NACL: trap
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@ NACL: encoding: [0xf0,0xde,0xfe,0xe7]
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trap
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trap
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@ CHECK: bx lr
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@ CHECK: bx lr
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