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Implement the first half of LiveDebugVariables.
Scan the MachineFunction for DBG_VALUE instructions, and replace them with a data structure similar to LiveIntervals. The live range of a DBG_VALUE is determined by propagating it down the dominator tree until a new DBG_VALUE is found. When a DBG_VALUE lives in a register, its live range is confined to the live range of the register's value. LiveDebugVariables runs before coalescing, so DBG_VALUEs are not artificially extended when registers are joined. The missing half will recreate DBG_VALUE instructions from the intervals when register allocation is complete. The pass is disabled by default. It can be enabled with the temporary command line option -live-debug-variables. llvm-svn: 120636
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@ -773,6 +773,20 @@ namespace llvm {
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};
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// Specialize IntervalMapInfo for half-open slot index intervals.
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template <typename> struct IntervalMapInfo;
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template <> struct IntervalMapInfo<SlotIndex> {
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static inline bool startLess(const SlotIndex &x, const SlotIndex &a) {
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return x < a;
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}
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static inline bool stopLess(const SlotIndex &b, const SlotIndex &x) {
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return b <= x;
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}
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static inline bool adjacent(const SlotIndex &a, const SlotIndex &b) {
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return a == b;
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}
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};
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}
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#endif // LLVM_CODEGEN_LIVEINDEX_H
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@ -19,32 +19,535 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "livedebug"
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#include "LiveDebugVariables.h"
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#include "llvm/Constants.h"
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#include "llvm/Metadata.h"
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#include "llvm/Value.h"
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#include "llvm/ADT/IntervalMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableLDV("live-debug-variables",
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cl::desc("Enable the live debug variables pass"), cl::Hidden);
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char LiveDebugVariables::ID = 0;
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INITIALIZE_PASS_BEGIN(LiveDebugVariables, "livedebugvars",
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"Debug Variable Analysis", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(LiveDebugVariables, "livedebugvars",
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"Debug Variable Analysis", false, false)
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void LiveDebugVariables::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineDominatorTree>();
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AU.addRequiredTransitive<LiveIntervals>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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LiveDebugVariables::LiveDebugVariables() : MachineFunctionPass(ID) {
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LiveDebugVariables::LiveDebugVariables() : MachineFunctionPass(ID), pImpl(0) {
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initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
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}
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bool LiveDebugVariables::runOnMachineFunction(MachineFunction &mf) {
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return false;
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/// Location - All the different places a user value can reside.
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/// Note that this includes immediate values that technically aren't locations.
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namespace {
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struct Location {
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/// kind - What kind of location is this?
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enum Kind {
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locUndef = 0,
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locImm = 0x80000000,
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locFPImm
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};
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/// Kind - One of the following:
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/// 1. locUndef
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/// 2. Register number (physical or virtual), data.SubIdx is the subreg index.
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/// 3. ~Frame index, data.Offset is the offset.
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/// 4. locImm, data.ImmVal is the constant integer value.
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/// 5. locFPImm, data.CFP points to the floating point constant.
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unsigned Kind;
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/// Data - Extra data about location.
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union {
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unsigned SubIdx; ///< For virtual registers.
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int64_t Offset; ///< For frame indices.
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int64_t ImmVal; ///< For locImm.
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const ConstantFP *CFP; ///< For locFPImm.
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} Data;
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Location(const MachineOperand &MO) {
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switch(MO.getType()) {
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case MachineOperand::MO_Register:
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Kind = MO.getReg();
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Data.SubIdx = MO.getSubReg();
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return;
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case MachineOperand::MO_Immediate:
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Kind = locImm;
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Data.ImmVal = MO.getImm();
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return;
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case MachineOperand::MO_FPImmediate:
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Kind = locFPImm;
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Data.CFP = MO.getFPImm();
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return;
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case MachineOperand::MO_FrameIndex:
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Kind = ~MO.getIndex();
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// FIXME: MO_FrameIndex should support an offset.
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Data.Offset = 0;
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return;
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default:
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Kind = locUndef;
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return;
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}
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}
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bool operator==(const Location &RHS) const {
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if (Kind != RHS.Kind)
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return false;
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switch (Kind) {
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case locUndef:
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return true;
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case locImm:
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return Data.ImmVal == RHS.Data.ImmVal;
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case locFPImm:
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return Data.CFP == RHS.Data.CFP;
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default:
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if (isReg())
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return Data.SubIdx == RHS.Data.SubIdx;
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else
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return Data.Offset == RHS.Data.Offset;
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}
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}
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/// isUndef - is this the singleton undef?
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bool isUndef() const { return Kind == locUndef; }
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/// isReg - is this a register location?
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bool isReg() const { return Kind && Kind < locImm; }
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void print(raw_ostream&, const TargetRegisterInfo*);
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};
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}
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/// LocMap - Map of where a user value is live, and its location.
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typedef IntervalMap<SlotIndex, unsigned, 4> LocMap;
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/// UserValue - A user value is a part of a debug info user variable.
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///
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/// A DBG_VALUE instruction notes that (a sub-register of) a virtual register
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/// holds part of a user variable. The part is identified by a byte offset.
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///
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/// UserValues are grouped into equivalence classes for easier searching. Two
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/// user values are related if they refer to the same variable, or if they are
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/// held by the same virtual register. The equivalence class is the transitive
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/// closure of that relation.
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namespace {
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class UserValue {
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const MDNode *variable; ///< The debug info variable we are part of.
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unsigned offset; ///< Byte offset into variable.
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UserValue *leader; ///< Equivalence class leader.
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UserValue *next; ///< Next value in equivalence class, or null.
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/// Numbered locations referenced by locmap.
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SmallVector<Location, 4> locations;
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/// Map of slot indices where this value is live.
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LocMap locInts;
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public:
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/// UserValue - Create a new UserValue.
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UserValue(const MDNode *var, unsigned o, LocMap::Allocator &alloc)
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: variable(var), offset(o), leader(this), next(0), locInts(alloc)
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{}
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/// getLeader - Get the leader of this value's equivalence class.
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UserValue *getLeader() {
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UserValue *l = leader;
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while (l != l->leader)
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l = l->leader;
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return leader = l;
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}
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/// getNext - Return the next UserValue in the equivalence class.
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UserValue *getNext() const { return next; }
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/// match - Does this UserValue match the aprameters?
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bool match(const MDNode *Var, unsigned Offset) const {
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return Var == variable && Offset == offset;
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}
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/// merge - Merge equivalence classes.
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static UserValue *merge(UserValue *L1, UserValue *L2) {
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L2 = L2->getLeader();
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if (!L1)
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return L2;
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L1 = L1->getLeader();
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if (L1 == L2)
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return L1;
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// Splice L2 before L1's members.
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UserValue *End = L2;
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while (End->next)
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End->leader = L1, End = End->next;
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End->leader = L1;
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End->next = L1->next;
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L1->next = L2;
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return L1;
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}
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/// getLocationNo - Return the location number that matches Loc.
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unsigned getLocationNo(Location Loc) {
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if (Loc.isUndef())
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return ~0u;
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unsigned n = std::find(locations.begin(), locations.end(), Loc) -
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locations.begin();
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if (n == locations.size())
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locations.push_back(Loc);
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return n;
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}
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/// addDef - Add a definition point to this value.
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void addDef(SlotIndex Idx, const MachineOperand &LocMO) {
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// Add a singular (Idx,Idx) -> Loc mapping.
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LocMap::iterator I = locInts.find(Idx);
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if (!I.valid() || I.start() != Idx)
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I.insert(Idx, Idx.getNextSlot(), getLocationNo(LocMO));
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}
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/// extendDef - Extend the current definition as far as possible down the
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/// dominator tree. Stop when meeting an existing def or when leaving the live
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/// range of VNI.
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/// @param Idx Starting point for the definition.
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/// @param LocNo Location number to propagate.
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/// @param LI Restrict liveness to where LI has the value VNI. May be null.
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/// @param VNI When LI is not null, this is the value to restrict to.
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/// @param LIS Live intervals analysis.
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/// @param MDT Dominator tree.
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void extendDef(SlotIndex Idx, unsigned LocNo,
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LiveInterval *LI, const VNInfo *VNI,
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LiveIntervals &LIS, MachineDominatorTree &MDT);
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/// computeIntervals - Compute the live intervals of all locations after
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/// collecting all their def points.
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void computeIntervals(LiveIntervals &LIS, MachineDominatorTree &MDT);
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void print(raw_ostream&, const TargetRegisterInfo*);
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};
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} // namespace
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/// LDVImpl - Implementation of the LiveDebugVariables pass.
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namespace {
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class LDVImpl {
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LiveDebugVariables &pass;
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LocMap::Allocator allocator;
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MachineFunction *MF;
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LiveIntervals *LIS;
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MachineDominatorTree *MDT;
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const TargetRegisterInfo *TRI;
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/// userValues - All allocated UserValue instances.
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SmallVector<UserValue*, 8> userValues;
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/// Map virtual register to eq class leader.
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typedef DenseMap<unsigned, UserValue*> VRMap;
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VRMap virtRegMap;
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/// Map user variable to eq class leader.
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typedef DenseMap<const MDNode *, UserValue*> UVMap;
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UVMap userVarMap;
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/// getUserValue - Find or create a UserValue.
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UserValue *getUserValue(const MDNode *Var, unsigned Offset);
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/// mapVirtReg - Map virtual register to an equivalence class.
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void mapVirtReg(unsigned VirtReg, UserValue *EC);
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/// handleDebugValue - Add DBG_VALUE instruction to our maps.
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/// @param MI DBG_VALUE instruction
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/// @param Idx Last valid SLotIndex before instruction.
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/// @return True if the DBG_VALUE instruction should be deleted.
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bool handleDebugValue(MachineInstr *MI, SlotIndex Idx);
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/// collectDebugValues - Collect and erase all DBG_VALUE instructions, adding
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/// a UserValue def for each instruction.
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/// @param mf MachineFunction to be scanned.
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/// @return True if any debug values were found.
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bool collectDebugValues(MachineFunction &mf);
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/// computeIntervals - Compute the live intervals of all user values after
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/// collecting all their def points.
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void computeIntervals();
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public:
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LDVImpl(LiveDebugVariables *ps) : pass(*ps) {}
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bool runOnMachineFunction(MachineFunction &mf);
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/// clear - Relase all memory.
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void clear() {
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DeleteContainerPointers(userValues);
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userValues.clear();
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virtRegMap.clear();
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userVarMap.clear();
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}
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void print(raw_ostream&);
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};
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} // namespace
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void Location::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
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switch (Kind) {
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case locUndef:
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OS << "undef";
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return;
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case locImm:
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OS << "int:" << Data.ImmVal;
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return;
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case locFPImm:
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OS << "fp:" << Data.CFP->getValueAPF().convertToDouble();
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return;
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default:
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if (isReg()) {
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if (TargetRegisterInfo::isVirtualRegister(Kind)) {
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OS << "%reg" << Kind;
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if (Data.SubIdx)
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OS << ':' << TRI->getSubRegIndexName(Data.SubIdx);
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} else
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OS << '%' << TRI->getName(Kind);
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} else {
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OS << "fi#" << ~Kind;
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if (Data.Offset)
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OS << '+' << Data.Offset;
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}
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return;
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}
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}
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void UserValue::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
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if (const MDString *MDS = dyn_cast<MDString>(variable->getOperand(2)))
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OS << "!\"" << MDS->getString() << "\"\t";
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if (offset)
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OS << '+' << offset;
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for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I) {
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OS << " [" << I.start() << ';' << I.stop() << "):";
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if (I.value() == ~0u)
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OS << "undef";
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else
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OS << I.value();
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}
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for (unsigned i = 0, e = locations.size(); i != e; ++i) {
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OS << " Loc" << i << '=';
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locations[i].print(OS, TRI);
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}
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OS << '\n';
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}
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void LDVImpl::print(raw_ostream &OS) {
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OS << "********** DEBUG VARIABLES **********\n";
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for (unsigned i = 0, e = userValues.size(); i != e; ++i)
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userValues[i]->print(OS, TRI);
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}
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UserValue *LDVImpl::getUserValue(const MDNode *Var, unsigned Offset) {
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UserValue *&Leader = userVarMap[Var];
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if (Leader) {
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UserValue *UV = Leader->getLeader();
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Leader = UV;
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for (; UV; UV = UV->getNext())
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if (UV->match(Var, Offset))
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return UV;
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}
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UserValue *UV = new UserValue(Var, Offset, allocator);
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userValues.push_back(UV);
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Leader = UserValue::merge(Leader, UV);
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return UV;
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}
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void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
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UserValue *&Leader = virtRegMap[VirtReg];
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Leader = UserValue::merge(Leader, EC);
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}
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bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) {
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// DBG_VALUE loc, offset, variable
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if (MI->getNumOperands() != 3 ||
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!MI->getOperand(1).isImm() || !MI->getOperand(2).isMetadata()) {
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DEBUG(dbgs() << "Can't handle " << *MI);
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return false;
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}
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// Get or create the UserValue for (variable,offset).
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unsigned Offset = MI->getOperand(1).getImm();
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const MDNode *Var = MI->getOperand(2).getMetadata();
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UserValue *UV = getUserValue(Var, Offset);
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// If the location is a virtual register, make sure it is mapped.
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if (MI->getOperand(0).isReg()) {
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unsigned Reg = MI->getOperand(0).getReg();
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if (Reg && TargetRegisterInfo::isVirtualRegister(Reg))
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mapVirtReg(Reg, UV);
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}
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UV->addDef(Idx, MI->getOperand(0));
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return true;
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}
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bool LDVImpl::collectDebugValues(MachineFunction &mf) {
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bool Changed = false;
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for (MachineFunction::iterator MFI = mf.begin(), MFE = mf.end(); MFI != MFE;
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++MFI) {
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MachineBasicBlock *MBB = MFI;
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for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
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MBBI != MBBE;) {
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if (!MBBI->isDebugValue()) {
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++MBBI;
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continue;
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}
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// DBG_VALUE has no slot index, use the previous instruction instead.
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SlotIndex Idx = MBBI == MBB->begin() ?
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LIS->getMBBStartIdx(MBB) :
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LIS->getInstructionIndex(llvm::prior(MBBI)).getDefIndex();
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// Handle consecutive DBG_VALUE instructions with the same slot index.
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do {
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if (handleDebugValue(MBBI, Idx)) {
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MBBI = MBB->erase(MBBI);
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Changed = true;
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} else
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++MBBI;
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} while (MBBI != MBBE && MBBI->isDebugValue());
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}
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}
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return Changed;
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}
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void UserValue::extendDef(SlotIndex Idx, unsigned LocNo,
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LiveInterval *LI, const VNInfo *VNI,
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LiveIntervals &LIS, MachineDominatorTree &MDT) {
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SmallVector<SlotIndex, 16> Todo;
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Todo.push_back(Idx);
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do {
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SlotIndex Start = Todo.pop_back_val();
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MachineBasicBlock *MBB = LIS.getMBBFromIndex(Start);
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SlotIndex Stop = LIS.getMBBEndIdx(MBB);
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LocMap::iterator I = locInts.find(Idx);
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// Limit to VNI's live range.
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bool ToEnd = true;
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if (LI && VNI) {
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LiveRange *Range = LI->getLiveRangeContaining(Start);
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if (!Range || Range->valno != VNI)
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continue;
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if (Range->end < Stop)
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Stop = Range->end, ToEnd = false;
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}
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// There could already be a short def at Start.
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if (I.valid() && I.start() <= Start) {
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// Stop when meeting a different location or an already extended interval.
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Start = Start.getNextSlot();
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if (I.value() != LocNo || I.stop() != Start)
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continue;
|
||||
// This is a one-slot placeholder. Just skip it.
|
||||
++I;
|
||||
}
|
||||
|
||||
// Limited by the next def.
|
||||
if (I.valid() && I.start() < Stop)
|
||||
Stop = I.start(), ToEnd = false;
|
||||
|
||||
if (Start >= Stop)
|
||||
continue;
|
||||
|
||||
I.insert(Start, Stop, LocNo);
|
||||
|
||||
// If we extended to the MBB end, propagate down the dominator tree.
|
||||
if (!ToEnd)
|
||||
continue;
|
||||
const std::vector<MachineDomTreeNode*> &Children =
|
||||
MDT.getNode(MBB)->getChildren();
|
||||
for (unsigned i = 0, e = Children.size(); i != e; ++i)
|
||||
Todo.push_back(LIS.getMBBStartIdx(Children[i]->getBlock()));
|
||||
} while (!Todo.empty());
|
||||
}
|
||||
|
||||
void
|
||||
UserValue::computeIntervals(LiveIntervals &LIS, MachineDominatorTree &MDT) {
|
||||
SmallVector<std::pair<SlotIndex, unsigned>, 16> Defs;
|
||||
|
||||
// Collect all defs to be extended (Skipping undefs).
|
||||
for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I)
|
||||
if (I.value() != ~0u)
|
||||
Defs.push_back(std::make_pair(I.start(), I.value()));
|
||||
|
||||
for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
|
||||
SlotIndex Idx = Defs[i].first;
|
||||
unsigned LocNo = Defs[i].second;
|
||||
const Location &Loc = locations[LocNo];
|
||||
|
||||
// Register locations are constrained to where the register value is live.
|
||||
if (Loc.isReg() && LIS.hasInterval(Loc.Kind)) {
|
||||
LiveInterval *LI = &LIS.getInterval(Loc.Kind);
|
||||
const VNInfo *VNI = LI->getVNInfoAt(Idx);
|
||||
extendDef(Idx, LocNo, LI, VNI, LIS, MDT);
|
||||
} else
|
||||
extendDef(Idx, LocNo, 0, 0, LIS, MDT);
|
||||
}
|
||||
|
||||
// Finally, erase all the undefs.
|
||||
for (LocMap::iterator I = locInts.begin(); I.valid();)
|
||||
if (I.value() == ~0u)
|
||||
I.erase();
|
||||
else
|
||||
++I;
|
||||
}
|
||||
|
||||
void LDVImpl::computeIntervals() {
|
||||
for (unsigned i = 0, e = userValues.size(); i != e; ++i)
|
||||
userValues[i]->computeIntervals(*LIS, *MDT);
|
||||
}
|
||||
|
||||
bool LDVImpl::runOnMachineFunction(MachineFunction &mf) {
|
||||
MF = &mf;
|
||||
LIS = &pass.getAnalysis<LiveIntervals>();
|
||||
MDT = &pass.getAnalysis<MachineDominatorTree>();
|
||||
TRI = mf.getTarget().getRegisterInfo();
|
||||
clear();
|
||||
DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
|
||||
<< ((Value*)mf.getFunction())->getName()
|
||||
<< " **********\n");
|
||||
|
||||
bool Changed = collectDebugValues(mf);
|
||||
computeIntervals();
|
||||
DEBUG(print(dbgs()));
|
||||
return Changed;
|
||||
}
|
||||
|
||||
bool LiveDebugVariables::runOnMachineFunction(MachineFunction &mf) {
|
||||
if (!EnableLDV)
|
||||
return false;
|
||||
if (!pImpl)
|
||||
pImpl = new LDVImpl(this);
|
||||
return static_cast<LDVImpl*>(pImpl)->runOnMachineFunction(mf);
|
||||
}
|
||||
|
||||
void LiveDebugVariables::releaseMemory() {
|
||||
if (pImpl)
|
||||
static_cast<LDVImpl*>(pImpl)->clear();
|
||||
}
|
||||
|
||||
LiveDebugVariables::~LiveDebugVariables() {
|
||||
if (pImpl)
|
||||
delete static_cast<LDVImpl*>(pImpl);
|
||||
}
|
||||
|
@ -31,6 +31,7 @@ public:
|
||||
static char ID; // Pass identification, replacement for typeid
|
||||
|
||||
LiveDebugVariables();
|
||||
~LiveDebugVariables();
|
||||
|
||||
/// renameRegister - Move any user variables in OldReg to NewReg:SubIdx.
|
||||
/// @param OldReg Old virtual register that is going away.
|
||||
@ -45,9 +46,8 @@ public:
|
||||
|
||||
private:
|
||||
|
||||
/// runOnMachineFunction - Analyze and remove DBG_VALUE instructions.
|
||||
virtual bool runOnMachineFunction(MachineFunction &);
|
||||
|
||||
virtual void releaseMemory();
|
||||
virtual void getAnalysisUsage(AnalysisUsage &) const;
|
||||
|
||||
};
|
||||
|
@ -15,6 +15,7 @@
|
||||
#define DEBUG_TYPE "regcoalescing"
|
||||
#include "SimpleRegisterCoalescing.h"
|
||||
#include "VirtRegMap.h"
|
||||
#include "LiveDebugVariables.h"
|
||||
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
||||
#include "llvm/Value.h"
|
||||
#include "llvm/Analysis/AliasAnalysis.h"
|
||||
@ -68,6 +69,7 @@ INITIALIZE_AG_PASS_BEGIN(SimpleRegisterCoalescing, RegisterCoalescer,
|
||||
"simple-register-coalescing", "Simple Register Coalescing",
|
||||
false, false, true)
|
||||
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
|
||||
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
|
||||
INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
|
||||
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
|
||||
INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
|
||||
@ -85,6 +87,8 @@ void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
|
||||
AU.addRequired<AliasAnalysis>();
|
||||
AU.addRequired<LiveIntervals>();
|
||||
AU.addPreserved<LiveIntervals>();
|
||||
AU.addRequired<LiveDebugVariables>();
|
||||
AU.addPreserved<LiveDebugVariables>();
|
||||
AU.addPreserved<SlotIndexes>();
|
||||
AU.addRequired<MachineLoopInfo>();
|
||||
AU.addPreserved<MachineLoopInfo>();
|
||||
@ -1626,6 +1630,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
|
||||
tri_ = tm_->getRegisterInfo();
|
||||
tii_ = tm_->getInstrInfo();
|
||||
li_ = &getAnalysis<LiveIntervals>();
|
||||
ldv_ = &getAnalysis<LiveDebugVariables>();
|
||||
AA = &getAnalysis<AliasAnalysis>();
|
||||
loopInfo = &getAnalysis<MachineLoopInfo>();
|
||||
|
||||
|
@ -21,7 +21,7 @@
|
||||
|
||||
namespace llvm {
|
||||
class SimpleRegisterCoalescing;
|
||||
class LiveVariables;
|
||||
class LiveDebugVariables;
|
||||
class TargetRegisterInfo;
|
||||
class TargetInstrInfo;
|
||||
class VirtRegMap;
|
||||
@ -44,6 +44,7 @@ namespace llvm {
|
||||
const TargetRegisterInfo* tri_;
|
||||
const TargetInstrInfo* tii_;
|
||||
LiveIntervals *li_;
|
||||
LiveDebugVariables *ldv_;
|
||||
const MachineLoopInfo* loopInfo;
|
||||
AliasAnalysis *AA;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user