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Optimization for certain shufflevector by using insertps.
Summary: If we're doing a v4f32/v4i32 shuffle on x86 with SSE4.1, we can lower certain shufflevectors to an insertps instruction: When most of the shufflevector result's elements come from one vector (and keep their index), and one element comes from another vector or a memory operand. Added tests for insertps optimizations on shufflevector. Added support and tests for v4i32 vector optimization. Reviewers: nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3475 llvm-svn: 207291
This commit is contained in:
Filipe Cabecinhas
parent
c54b3a7e23
commit
54c5ad74d7
@ -3931,6 +3931,29 @@ static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
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return true;
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}
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/// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to INSERTPS.
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/// i. e: If all but one element come from the same vector.
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static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
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// TODO: Deal with AVX's VINSERTPS
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if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
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return false;
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unsigned CorrectPosV1 = 0;
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unsigned CorrectPosV2 = 0;
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for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i)
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if (Mask[i] == i)
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++CorrectPosV1;
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else if (Mask[i] == i + 4)
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++CorrectPosV2;
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if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
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// We have 3 elements from one vector, and one from another.
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return true;
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return false;
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}
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//
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// Some special combinations that can be optimized.
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//
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@ -7263,6 +7286,84 @@ SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
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getShuffleSHUFImmediate(SVOp), DAG);
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}
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// It is only safe to call this function if isINSERTPSMask is true for
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// this shufflevector mask.
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static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
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SelectionDAG &DAG) {
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// Generate an insertps instruction when inserting an f32 from memory onto a
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// v4f32 or when copying a member from one v4f32 to another.
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// We also use it for transferring i32 from one register to another,
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// since it simply copies the same bits.
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// If we're transfering an i32 from memory to a specific element in a
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// register, we output a generic DAG that will match the PINSRD
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// instruction.
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// TODO: Optimize for AVX cases too (VINSERTPS)
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MVT VT = SVOp->getSimpleValueType(0);
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MVT EVT = VT.getVectorElementType();
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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auto Mask = SVOp->getMask();
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assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
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"unsupported vector type for insertps/pinsrd");
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int FromV1 = std::count_if(Mask.begin(), Mask.end(),
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[](const int &i) { return i < 4; });
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SDValue From;
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SDValue To;
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unsigned DestIndex;
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if (FromV1 == 1) {
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From = V1;
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To = V2;
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DestIndex = std::find_if(Mask.begin(), Mask.end(),
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[](const int &i) { return i < 4; }) -
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Mask.begin();
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} else {
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From = V2;
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To = V1;
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DestIndex = std::find_if(Mask.begin(), Mask.end(),
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[](const int &i) { return i >= 4; }) -
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Mask.begin();
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}
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if (MayFoldLoad(From)) {
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// Trivial case, when From comes from a load and is only used by the
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// shuffle. Make it use insertps from the vector that we need from that
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// load.
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SDValue Addr = From.getOperand(1);
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SDValue NewAddr =
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DAG.getNode(ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
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DAG.getConstant(DestIndex * EVT.getStoreSize(),
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Addr.getSimpleValueType()));
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LoadSDNode *Load = cast<LoadSDNode>(From);
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SDValue NewLoad =
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DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
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DAG.getMachineFunction().getMachineMemOperand(
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Load->getMemOperand(), 0, EVT.getStoreSize()));
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if (EVT == MVT::f32) {
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// Create this as a scalar to vector to match the instruction pattern.
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SDValue LoadScalarToVector =
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DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
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SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
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return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
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InsertpsMask);
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} else { // EVT == MVT::i32
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// If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
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// instruction, to match the PINSRD instruction, which loads an i32 to a
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// certain vector element.
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return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
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DAG.getConstant(DestIndex, MVT::i32));
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}
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}
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// Vector-element-to-vector
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unsigned SrcIndex = Mask[DestIndex] % 4;
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SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
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return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
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}
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// Reduce a vector shuffle to zext.
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static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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@ -7674,6 +7775,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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if (BlendOp.getNode())
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return BlendOp;
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if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
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return getINSERTPS(SVOp, dl, DAG);
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unsigned Imm8;
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if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
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return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s -check-prefix=X32 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s -check-prefix=X64 --check-prefix=CHECK
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@g16 = external global i16
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@ -249,3 +249,74 @@ entry:
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; X64: ret
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}
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define <4 x float> @insertps_from_shufflevector_1(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
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entry:
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%0 = load <4 x float>* %pb, align 16
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%vecinit6 = shufflevector <4 x float> %a, <4 x float> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x float> %vecinit6
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; CHECK-LABEL: insertps_from_shufflevector_1:
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; CHECK-NOT: shufps
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; CHECK: insertps $48,
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; CHECK: ret
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}
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define <4 x float> @insertps_from_shufflevector_2(<4 x float> %a, <4 x float> %b) {
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entry:
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%vecinit6 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
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ret <4 x float> %vecinit6
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; CHECK-LABEL: insertps_from_shufflevector_2:
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; CHECK-NOT: mov
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; CHECK-NOT: shufps
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; CHECK: insertps $96,
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; CHECK: ret
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}
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; For loading an i32 from memory into an xmm register we use pinsrd
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; instead of insertps
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define <4 x i32> @pinsrd_from_shufflevector_i32(<4 x i32> %a, <4 x i32>* nocapture readonly %pb) {
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entry:
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%0 = load <4 x i32>* %pb, align 16
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%vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x i32> %vecinit6
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; CHECK-LABEL: pinsrd_from_shufflevector_i32:
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; CHECK-NOT: mov
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; CHECK-NOT: shufps
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; CHECK: pinsrd $3,
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; CHECK: ret
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}
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define <4 x i32> @insertps_from_shufflevector_i32_2(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
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ret <4 x i32> %vecinit6
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; CHECK-LABEL: insertps_from_shufflevector_i32_2:
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; CHECK-NOT: mov
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; CHECK-NOT: shufps
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; CHECK: insertps $208,
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; CHECK: ret
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}
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define <4 x float> @insertps_from_load_ins_elt_undef(<4 x float> %a, float* %b) {
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; CHECK-LABEL: insertps_from_load_ins_elt_undef:
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; CHECK-NOT: mov
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; CHECK-NOT: shufps
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; CHECK: insertps $16,
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; CHECK: ret
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%1 = load float* %b, align 4
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%2 = insertelement <4 x float> undef, float %1, i32 0
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%result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
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ret <4 x float> %result
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}
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define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
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; CHECK-LABEL: insertps_from_load_ins_elt_undef_i32:
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; TODO: Like on pinsrd_from_shufflevector_i32, remove this mov instr
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;; aCHECK-NOT: mov
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; CHECK-NOT: shufps
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; CHECK: insertps $32,
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; CHECK: ret
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%1 = load i32* %b, align 4
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%2 = insertelement <4 x i32> undef, i32 %1, i32 0
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%result = shufflevector <4 x i32> %a, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
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ret <4 x i32> %result
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}
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