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Fix a minor bug in previous checking
Enable folding of long seteq/setne comparisons into branches and select instructions Implement unfolded long relational comparisons against a constants a bit more efficiently Folding comparisons changes code that looks like this: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] mov %ECX, %EAX or %ECX, %EDX sete %CL test %CL, %CL je .LBB2 # PC rel: F into code that looks like this: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] mov %ECX, %EAX or %ECX, %EDX jne .LBB2 # PC rel: F This speeds up 186.crafty by 6% with llc-ls. llvm-svn: 12702
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@ -756,7 +756,9 @@ static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
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Instruction *User = cast<Instruction>(SCI->use_back());
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if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
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SCI->getParent() == User->getParent() &&
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getClassB(SCI->getOperand(0)->getType()) != cLong)
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(getClassB(SCI->getOperand(0)->getType()) != cLong ||
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SCI->getOpcode() == Instruction::SetEQ ||
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SCI->getOpcode() == Instruction::SetNE))
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return SCI;
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}
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return 0;
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@ -846,11 +848,36 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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unsigned HiTmp = Op0r+1;
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if (HiCst != 0) {
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HiTmp = makeAnotherReg(Type::IntTy);
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BuildMI(*MBB, IP, X86::XOR32rr, 2,HiTmp).addReg(Op0r+1).addImm(HiCst);
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BuildMI(*MBB, IP, X86::XOR32ri, 2,HiTmp).addReg(Op0r+1).addImm(HiCst);
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}
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unsigned FinalTmp = makeAnotherReg(Type::IntTy);
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BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
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return OpNum;
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} else {
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// Emit a sequence of code which compares the high and low parts once
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// each, then uses a conditional move to handle the overflow case. For
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// example, a setlt for long would generate code like this:
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//
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// AL = lo(op1) < lo(op2) // Signedness depends on operands
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// BL = hi(op1) < hi(op2) // Always unsigned comparison
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// dest = hi(op1) == hi(op2) ? AL : BL;
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//
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// FIXME: This would be much better if we had hierarchical register
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// classes! Until then, hardcode registers so that we can deal with
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// their aliases (because we don't have conditional byte moves).
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//
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BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(LowCst);
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BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
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BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r+1).addImm(HiCst);
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BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0,X86::BL);
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BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
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BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
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BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
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.addReg(X86::AX);
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// NOTE: visitSetCondInst knows that the value is dumped into the BL
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// register at this point for long values...
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return OpNum;
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}
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}
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}
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