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R600: Match sign_extend_inreg to BFE instructions
llvm-svn: 204072
This commit is contained in:
Matt Arsenault
parent
c95c06bda9
commit
553297669c
@ -211,6 +211,20 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FSUB, VT, Expand);
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setOperationAction(ISD::SELECT, VT, Expand);
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}
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
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}
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//===----------------------------------------------------------------------===//
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@ -927,6 +941,101 @@ SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
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}
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SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
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unsigned BitsDiff,
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SelectionDAG &DAG) const {
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MVT VT = Op.getSimpleValueType();
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SDLoc DL(Op);
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SDValue Shift = DAG.getConstant(BitsDiff, VT);
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// Shift left by 'Shift' bits.
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SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
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// Signed shift Right by 'Shift' bits.
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return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
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}
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SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
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SelectionDAG &DAG) const {
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EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
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MVT VT = Op.getSimpleValueType();
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MVT ScalarVT = VT.getScalarType();
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unsigned SrcBits = ExtraVT.getScalarType().getSizeInBits();
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unsigned DestBits = ScalarVT.getSizeInBits();
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unsigned BitsDiff = DestBits - SrcBits;
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if (!Subtarget->hasBFE())
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return ExpandSIGN_EXTEND_INREG(Op, BitsDiff, DAG);
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SDValue Src = Op.getOperand(0);
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if (VT.isVector()) {
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SDLoc DL(Op);
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// Need to scalarize this, and revisit each of the scalars later.
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// TODO: Don't scalarize on Evergreen?
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unsigned NElts = VT.getVectorNumElements();
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SmallVector<SDValue, 8> Args;
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ExtractVectorElements(Src, DAG, Args, 0, NElts);
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SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
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for (unsigned I = 0; I < NElts; ++I)
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Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
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return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args.data(), Args.size());
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}
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if (SrcBits == 32) {
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SDLoc DL(Op);
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// If the source is 32-bits, this is really half of a 2-register pair, and
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// we need to discard the unused half of the pair.
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SDValue TruncSrc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Src);
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return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, TruncSrc);
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}
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unsigned NElts = VT.isVector() ? VT.getVectorNumElements() : 1;
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// TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
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// might not be worth the effort, and will need to expand to shifts when
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// fixing SGPR copies.
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if (SrcBits < 32 && DestBits <= 32) {
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SDLoc DL(Op);
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MVT ExtVT = (NElts == 1) ? MVT::i32 : MVT::getVectorVT(MVT::i32, NElts);
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if (DestBits != 32)
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Src = DAG.getNode(ISD::ZERO_EXTEND, DL, ExtVT, Src);
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// FIXME: This should use TargetConstant, but that hits assertions for
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// Evergreen.
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SDValue Ext = DAG.getNode(AMDGPUISD::BFE_I32, DL, ExtVT,
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Op.getOperand(0), // Operand
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DAG.getConstant(0, ExtVT), // Offset
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DAG.getConstant(SrcBits, ExtVT)); // Width
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// Truncate to the original type if necessary.
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if (ScalarVT == MVT::i32)
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return Ext;
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return DAG.getNode(ISD::TRUNCATE, DL, VT, Ext);
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}
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// For small types, extend to 32-bits first.
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if (SrcBits < 32) {
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SDLoc DL(Op);
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MVT ExtVT = (NElts == 1) ? MVT::i32 : MVT::getVectorVT(MVT::i32, NElts);
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SDValue TruncSrc = DAG.getNode(ISD::TRUNCATE, DL, ExtVT, Src);
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SDValue Ext32 = DAG.getNode(AMDGPUISD::BFE_I32,
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DL,
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ExtVT,
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TruncSrc, // Operand
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DAG.getConstant(0, ExtVT), // Offset
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DAG.getConstant(SrcBits, ExtVT)); // Width
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return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Ext32);
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}
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// For everything else, use the standard bitshift expansion.
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return ExpandSIGN_EXTEND_INREG(Op, BitsDiff, DAG);
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}
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//===----------------------------------------------------------------------===//
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// Helper functions
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//===----------------------------------------------------------------------===//
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@ -1019,6 +1128,8 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(FMIN)
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NODE_NAME_CASE(SMIN)
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NODE_NAME_CASE(UMIN)
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NODE_NAME_CASE(BFE_U32)
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NODE_NAME_CASE(BFE_I32)
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NODE_NAME_CASE(URECIP)
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NODE_NAME_CASE(DOT4)
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NODE_NAME_CASE(EXPORT)
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@ -142,6 +142,10 @@ private:
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SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
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unsigned BitsDiff,
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SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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@ -171,6 +175,8 @@ enum {
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UMIN,
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URECIP,
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DOT4,
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BFE_U32, // Extract range of bits with zero extension to 32-bits.
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BFE_I32, // Extract range of bits with sign extension to 32-bits.
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TEXTURE_FETCH,
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EXPORT,
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CONST_ADDRESS,
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@ -86,3 +86,7 @@ def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
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def AMDGPUround : SDNode<"ISD::FROUND",
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
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def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
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@ -68,6 +68,15 @@ public:
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enum Generation getGeneration() const;
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bool hasHWFP64() const;
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bool hasCaymanISA() const;
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFM() const {
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return hasBFE();
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}
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bool IsIRStructurizerEnabled() const;
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bool isIfCvtEnabled() const;
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unsigned getWavefrontSize() const;
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@ -94,9 +94,6 @@ void AMDGPUTargetLowering::InitAMDILLowering() {
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for (unsigned int x = 0; x < NumTypes; ++x) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
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//FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
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// We cannot sextinreg, expand to shifts
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setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
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setOperationAction(ISD::SUBE, VT, Expand);
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setOperationAction(ISD::SUBC, VT, Expand);
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setOperationAction(ISD::ADDE, VT, Expand);
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@ -191,14 +188,12 @@ void AMDGPUTargetLowering::InitAMDILLowering() {
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setOperationAction(ISD::UDIV, MVT::v4i8, Expand);
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setOperationAction(ISD::UDIV, MVT::v2i16, Expand);
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setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
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setOperationAction(ISD::SUBC, MVT::Other, Expand);
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setOperationAction(ISD::ADDE, MVT::Other, Expand);
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setOperationAction(ISD::ADDC, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
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// Use the default implementation.
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@ -322,36 +317,6 @@ AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
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return DST;
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}
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SDValue
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AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const {
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SDValue Data = Op.getOperand(0);
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VTSDNode *BaseType = cast<VTSDNode>(Op.getOperand(1));
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SDLoc DL(Op);
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EVT DVT = Data.getValueType();
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EVT BVT = BaseType->getVT();
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unsigned baseBits = BVT.getScalarType().getSizeInBits();
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unsigned srcBits = DVT.isSimple() ? DVT.getScalarType().getSizeInBits() : 1;
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unsigned shiftBits = srcBits - baseBits;
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if (srcBits < 32) {
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// If the op is less than 32 bits, then it needs to extend to 32bits
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// so it can properly keep the upper bits valid.
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EVT IVT = genIntType(32, DVT.isVector() ? DVT.getVectorNumElements() : 1);
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Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data);
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shiftBits = 32 - baseBits;
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DVT = IVT;
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}
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SDValue Shift = DAG.getConstant(shiftBits, DVT);
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// Shift left by 'Shift' bits.
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Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift);
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// Signed shift Right by 'Shift' bits.
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Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
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if (srcBits < 32) {
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// Once the sign extension is done, the op needs to be converted to
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// its original type.
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Data = DAG.getSExtOrTrunc(Data, DL, Op.getOperand(0).getValueType());
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}
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return Data;
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}
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EVT
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AMDGPUTargetLowering::genIntType(uint32_t size, uint32_t numEle) const {
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int iSize = (size * numEle);
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@ -68,10 +68,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
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let TargetPrefix = "AMDIL", isTarget = 1 in {
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def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
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def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">,
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TernaryIntInt;
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def int_AMDIL_bit_extract_u32 : GCCBuiltin<"__amdil_ubit_extract">,
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TernaryIntInt;
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def int_AMDIL_bit_reverse_u32 : GCCBuiltin<"__amdil_ubit_reverse">,
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UnaryIntInt;
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def int_AMDIL_bit_count_i32 : GCCBuiltin<"__amdil_count_bits">,
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@ -1383,6 +1383,11 @@ SDValue R600TargetLowering::LowerFormalArguments(
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PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
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AMDGPUAS::CONSTANT_BUFFER_0);
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// i64 isn't a legal type, so the register type used ends up as i32, which
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// isn't expected here. It attempts to create this sextload, but it ends up
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// being invalid. Somehow this seems to work with i64 arguments, but breaks
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// for <1 x i64>.
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// The first 36 bytes of the input buffer contains information about
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// thread group and global sizes.
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SDValue Arg = DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, Chain,
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@ -1517,15 +1517,20 @@ let Predicates = [isEGorCayman] in {
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// Example Usage:
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// (Offset, Width)
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//
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// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
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// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
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// (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
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// (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
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// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
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// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
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// (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
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// (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
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def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
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[(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
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i32:$src2))],
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[(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
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VecALU
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>;
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def BFE_INT_eg : R600_3OP <0x4, "BFE_INT",
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[(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
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VecALU
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>;
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// XXX: This pattern is broken, disabling for now. See comment in
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// AMDGPUInstructions.td for more info.
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// def : BFEPattern <BFE_UINT_eg>;
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@ -1074,8 +1074,14 @@ def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
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def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
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def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
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def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
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def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
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def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
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let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
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def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
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[(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
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def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
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[(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
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}
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def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
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defm : BFIPatterns <V_BFI_B32>;
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def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
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@ -26,14 +26,11 @@ entry:
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; The order of A and B does not matter.
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; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
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; The result must be sign-extended
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; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x
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; EG-CHECK: 16
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; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
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; EG-CHECK: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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; EG-CHECK: 16
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; SI-CHECK-LABEL: @i16_mad24
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; SI-CHECK: V_MAD_U32_U24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 16, [[MAD]]
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; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 16, [[LSHL]]
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; SI-CHECK: V_BFE_I32 v{{[0-9]}}, [[MAD]], 0, 16
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define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
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entry:
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@ -51,14 +48,11 @@ entry:
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; The order of A and B does not matter.
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; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
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; The result must be sign-extended
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; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x
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; EG-CHECK: 24
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; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
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; EG-CHECK: 24
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; EG-CHECK: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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; EG-CHECK: 8
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; SI-CHECK-LABEL: @i8_mad24
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; SI-CHECK: V_MAD_U32_U24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 24, [[MUL]]
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; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 24, [[LSHL]]
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; SI-CHECK: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8
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define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
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entry:
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@ -24,15 +24,11 @@ entry:
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; The order of A and B does not matter.
|
||||
; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]]
|
||||
; The result must be sign-extended
|
||||
; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x
|
||||
; EG-CHECK: 16
|
||||
; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
|
||||
; EG-CHECK: BFE_INT {{[* ]*}}T{{[0-9]}}.{{[XYZW]}}, PV.[[MUL_CHAN]], 0.0, literal.x
|
||||
; EG-CHECK: 16
|
||||
; SI-CHECK-LABEL: @i16_mul24
|
||||
; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
|
||||
; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 16, [[MUL]]
|
||||
; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 16, [[LSHL]]
|
||||
|
||||
; SI-CHECK: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 16,
|
||||
define void @i16_mul24(i32 addrspace(1)* %out, i16 %a, i16 %b) {
|
||||
entry:
|
||||
%0 = mul i16 %a, %b
|
||||
@ -47,14 +43,10 @@ entry:
|
||||
; The order of A and B does not matter.
|
||||
; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]]
|
||||
; The result must be sign-extended
|
||||
; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x
|
||||
; EG-CHECK: 24
|
||||
; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
|
||||
; EG-CHECK: 24
|
||||
; EG-CHECK: BFE_INT {{[* ]*}}T{{[0-9]}}.{{[XYZW]}}, PV.[[MUL_CHAN]], 0.0, literal.x
|
||||
; SI-CHECK-LABEL: @i8_mul24
|
||||
; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
|
||||
; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 24, [[MUL]]
|
||||
; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 24, [[LSHL]]
|
||||
; SI-CHECK: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8,
|
||||
|
||||
define void @i8_mul24(i32 addrspace(1)* %out, i8 %a, i8 %b) {
|
||||
entry:
|
||||
|
||||
236
test/CodeGen/R600/sext-in-reg.ll
Normal file
236
test/CodeGen/R600/sext-in-reg.ll
Normal file
@ -0,0 +1,236 @@
|
||||
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_i1_i32
|
||||
; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
|
||||
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[ARG]], 0, 1
|
||||
; SI: BUFFER_STORE_DWORD [[EXTRACT]],
|
||||
|
||||
; EG: BFE_INT
|
||||
define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) {
|
||||
%shl = shl i32 %in, 31
|
||||
%sext = ashr i32 %shl, 31
|
||||
store i32 %sext, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_i8_to_i32
|
||||
; SI: S_ADD_I32 [[VAL:s[0-9]+]],
|
||||
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 8
|
||||
; SI: BUFFER_STORE_DWORD [[EXTRACT]],
|
||||
|
||||
; EG: BFE_INT
|
||||
define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
|
||||
%c = add i32 %a, %b ; add to prevent folding into extload
|
||||
%shl = shl i32 %c, 24
|
||||
%ashr = ashr i32 %shl, 24
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_i16_to_i32
|
||||
; SI: S_ADD_I32 [[VAL:s[0-9]+]],
|
||||
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 16
|
||||
; SI: BUFFER_STORE_DWORD [[EXTRACT]],
|
||||
|
||||
; EG: BFE_INT
|
||||
define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
|
||||
%c = add i32 %a, %b ; add to prevent folding into extload
|
||||
%shl = shl i32 %c, 16
|
||||
%ashr = ashr i32 %shl, 16
|
||||
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_i8_to_v1i32
|
||||
; SI: S_ADD_I32 [[VAL:s[0-9]+]],
|
||||
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 8
|
||||
; SI: BUFFER_STORE_DWORD [[EXTRACT]],
|
||||
|
||||
; EG: BFE_INT
|
||||
define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind {
|
||||
%c = add <1 x i32> %a, %b ; add to prevent folding into extload
|
||||
%shl = shl <1 x i32> %c, <i32 24>
|
||||
%ashr = ashr <1 x i32> %shl, <i32 24>
|
||||
store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_i8_to_i64
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
|
||||
; SI: BUFFER_STORE_DWORD
|
||||
|
||||
; EG: BFE_INT
|
||||
; EG: ASHR
|
||||
define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
|
||||
%c = add i64 %a, %b
|
||||
%shl = shl i64 %c, 56
|
||||
%ashr = ashr i64 %shl, 56
|
||||
store i64 %ashr, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_i16_to_i64
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 16
|
||||
; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
|
||||
; SI: BUFFER_STORE_DWORD
|
||||
|
||||
; EG: BFE_INT
|
||||
; EG: ASHR
|
||||
define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
|
||||
%c = add i64 %a, %b
|
||||
%shl = shl i64 %c, 48
|
||||
%ashr = ashr i64 %shl, 48
|
||||
store i64 %ashr, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments.
|
||||
; XFUNC-LABEL: @sext_in_reg_i8_to_v1i64
|
||||
; XSI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; XSI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
|
||||
; XSI: BUFFER_STORE_DWORD
|
||||
; XEG: BFE_INT
|
||||
; XEG: ASHR
|
||||
; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) nounwind {
|
||||
; %c = add <1 x i64> %a, %b
|
||||
; %shl = shl <1 x i64> %c, <i64 56>
|
||||
; %ashr = ashr <1 x i64> %shl, <i64 56>
|
||||
; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8
|
||||
; ret void
|
||||
; }
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_i1_in_i32_other_amount
|
||||
; SI-NOT: BFE
|
||||
; SI: S_LSHL_B32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6
|
||||
; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG]], 7
|
||||
; EG-NOT: BFE
|
||||
define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
|
||||
%c = add i32 %a, %b
|
||||
%x = shl i32 %c, 6
|
||||
%y = ashr i32 %x, 7
|
||||
store i32 %y, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount
|
||||
; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
|
||||
; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
|
||||
; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
|
||||
; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
|
||||
; EG-NOT: BFE
|
||||
define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
|
||||
%c = add <2 x i32> %a, %b
|
||||
%x = shl <2 x i32> %c, <i32 6, i32 6>
|
||||
%y = ashr <2 x i32> %x, <i32 7, i32 7>
|
||||
store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_v2i1_to_v2i32
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
|
||||
; SI: BUFFER_STORE_DWORDX2
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
|
||||
%c = add <2 x i32> %a, %b ; add to prevent folding into extload
|
||||
%shl = shl <2 x i32> %c, <i32 31, i32 31>
|
||||
%ashr = ashr <2 x i32> %shl, <i32 31, i32 31>
|
||||
store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_v4i1_to_v4i32
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
|
||||
; SI: BUFFER_STORE_DWORDX4
|
||||
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
|
||||
%c = add <4 x i32> %a, %b ; add to prevent folding into extload
|
||||
%shl = shl <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
|
||||
%ashr = ashr <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>
|
||||
store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_v2i8_to_v2i32
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: BUFFER_STORE_DWORDX2
|
||||
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
|
||||
%c = add <2 x i32> %a, %b ; add to prevent folding into extload
|
||||
%shl = shl <2 x i32> %c, <i32 24, i32 24>
|
||||
%ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
|
||||
store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_v4i8_to_v4i32
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: BUFFER_STORE_DWORDX4
|
||||
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
|
||||
%c = add <4 x i32> %a, %b ; add to prevent folding into extload
|
||||
%shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
|
||||
%ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
|
||||
store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @sext_in_reg_v2i16_to_v2i32
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
|
||||
; SI: BUFFER_STORE_DWORDX2
|
||||
|
||||
; EG: BFE
|
||||
; EG: BFE
|
||||
define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
|
||||
%c = add <2 x i32> %a, %b ; add to prevent folding into extload
|
||||
%shl = shl <2 x i32> %c, <i32 24, i32 24>
|
||||
%ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
|
||||
store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @testcase
|
||||
define void @testcase(i8 addrspace(1)* %out, i8 %a) nounwind {
|
||||
%and_a_1 = and i8 %a, 1
|
||||
%cmp_eq = icmp eq i8 %and_a_1, 0
|
||||
%cmp_slt = icmp slt i8 %a, 0
|
||||
%sel0 = select i1 %cmp_slt, i8 0, i8 %a
|
||||
%sel1 = select i1 %cmp_eq, i8 0, i8 %a
|
||||
%xor = xor i8 %sel0, %sel1
|
||||
store i8 %xor, i8 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @testcase_3
|
||||
define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind {
|
||||
%and_a_1 = and i8 %a, 1
|
||||
%cmp_eq = icmp eq i8 %and_a_1, 0
|
||||
%cmp_slt = icmp slt i8 %a, 0
|
||||
%sel0 = select i1 %cmp_slt, i8 0, i8 %a
|
||||
%sel1 = select i1 %cmp_eq, i8 0, i8 %a
|
||||
%xor = xor i8 %sel0, %sel1
|
||||
store i8 %xor, i8 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
17
test/CodeGen/R600/v1i64-kernel-arg.ll
Normal file
17
test/CodeGen/R600/v1i64-kernel-arg.ll
Normal file
@ -0,0 +1,17 @@
|
||||
; REQUIRES: asserts
|
||||
; XFAIL: *
|
||||
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: @kernel_arg_i64
|
||||
define void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind {
|
||||
store i64 %a, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; i64 arg works, v1i64 arg does not.
|
||||
; CHECK-LABEL: @kernel_arg_v1i64
|
||||
define void @kernel_arg_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a) nounwind {
|
||||
store <1 x i64> %a, <1 x i64> addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user