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Represent tADDspi and tSUBspi as two-address instructions.

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llvm-svn: 33551
This commit is contained in:
Evan Cheng 2007-01-26 21:33:19 +00:00
parent 64f4242072
commit 55455f0532
2 changed files with 5 additions and 5 deletions
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8
lib/Target/ARM/ARMInstrThumb.td
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@ -285,8 +285,8 @@ def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
"add $dst, pc, $rhs * 4", []>;
def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
"add $dst, $sp, $rhs * 4", []>;
def tADDspi : TI<(ops GPR:$sp, i32imm:$rhs),
"add $sp, $rhs * 4", []>;
def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
"add $dst, $rhs * 4", []>;
def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
@ -413,8 +413,8 @@ def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
"sub $dst, $lhs, $rhs",
[(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
def tSUBspi : TI<(ops GPR:$sp, i32imm:$rhs),
"sub $sp, $rhs * 4", []>;
def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
"sub $dst, $rhs * 4", []>;
def tSXTB : TI<(ops GPR:$dst, GPR:$src),
"sxtb $dst, $src",

2
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -378,7 +378,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
Bytes -= ThisVal;
// Build the new tADD / tSUB.
if (isTwoAddr)
BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addImm(ThisVal);
BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
else {
BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal);
BaseReg = DestReg;