RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 20:12:56 +02:00
Code Issues Projects Releases Wiki Activity

Use the TargetMachine on the DAG or the MachineFunction instead

Browse Source 
of using the cached TargetMachine.

llvm-svn: 210589
This commit is contained in:
Eric Christopher 2014-06-10 21:25:13 +00:00
parent 9f0e1d4d7f
commit 5550b48a00
1 changed files with 81 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

164
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1732,7 +1732,7 @@ const MCExpr *
X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
const MachineBasicBlock *MBB, const MachineBasicBlock *MBB,
unsigned uid,MCContext &Ctx) const{ unsigned uid,MCContext &Ctx) const{
assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
Subtarget->isPICStyleGOT()); Subtarget->isPICStyleGOT());
// In 32-bit ELF systems, our jump table entries are formed with @GOTOFF // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
// entries. // entries.
@ -1831,7 +1831,7 @@ X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const { LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
RVLocs, Context); RVLocs, Context);
return CCInfo.CheckReturn(Outs, RetCC_X86); return CCInfo.CheckReturn(Outs, RetCC_X86);
} }
@ -1851,7 +1851,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
RVLocs, *DAG.getContext()); RVLocs, *DAG.getContext());
CCInfo.AnalyzeReturn(Outs, RetCC_X86); CCInfo.AnalyzeReturn(Outs, RetCC_X86);
@ -2023,7 +2023,7 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
bool Is64Bit = Subtarget->is64Bit(); bool Is64Bit = Subtarget->is64Bit();
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
getTargetMachine(), RVLocs, *DAG.getContext()); DAG.getTarget(), RVLocs, *DAG.getContext());
CCInfo.AnalyzeCallResult(Ins, RetCC_X86); CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
// Copy all of the result registers out of their specified physreg. // Copy all of the result registers out of their specified physreg.
@ -2173,8 +2173,8 @@ X86TargetLowering::LowerMemArgument(SDValue Chain,
unsigned i) const { unsigned i) const {
// Create the nodes corresponding to a load from this parameter slot. // Create the nodes corresponding to a load from this parameter slot.
ISD::ArgFlagsTy Flags = Ins[i].Flags; ISD::ArgFlagsTy Flags = Ins[i].Flags;
bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
getTargetMachine().Options.GuaranteedTailCallOpt); CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
EVT ValVT; EVT ValVT;
@ -2231,7 +2231,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
// Assign locations to all of the incoming arguments. // Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
ArgLocs, *DAG.getContext()); ArgLocs, *DAG.getContext());
// Allocate shadow area for Win64 // Allocate shadow area for Win64
@ -2395,7 +2395,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
TotalNumXMMRegs = 0; TotalNumXMMRegs = 0;
if (IsWin64) { if (IsWin64) {
const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
// Get to the caller-allocated home save location. Add 8 to account // Get to the caller-allocated home save location. Add 8 to account
// for the return address. // for the return address.
int HomeOffset = TFI.getOffsetOfLocalArea() + 8; int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
@ -2594,7 +2594,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Analyze operands of the call, assigning locations to each operand. // Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
ArgLocs, *DAG.getContext()); ArgLocs, *DAG.getContext());
// Allocate shadow area for Win64 // Allocate shadow area for Win64
@ -2609,7 +2609,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// This is a sibcall. The memory operands are available in caller's // This is a sibcall. The memory operands are available in caller's
// own caller's stack. // own caller's stack.
NumBytes = 0; NumBytes = 0;
else if (getTargetMachine().Options.GuaranteedTailCallOpt && else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
IsTailCallConvention(CallConv)) IsTailCallConvention(CallConv))
NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
@ -2656,7 +2656,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Walk the register/memloc assignments, inserting copies/loads. In the case // Walk the register/memloc assignments, inserting copies/loads. In the case
// of tail call optimization arguments are handle later. // of tail call optimization arguments are handle later.
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
// Skip inalloca arguments, they have already been written. // Skip inalloca arguments, they have already been written.
ISD::ArgFlagsTy Flags = Outs[i].Flags; ISD::ArgFlagsTy Flags = Outs[i].Flags;
@ -2847,7 +2847,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
} }
if (getTargetMachine().getCodeModel() == CodeModel::Large) { if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
assert(Is64Bit && "Large code model is only legal in 64-bit mode."); assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
// In the 64-bit large code model, we have to make all calls // In the 64-bit large code model, we have to make all calls
// through a register, since the call instruction's 32-bit // through a register, since the call instruction's 32-bit
@ -2871,7 +2871,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// has hidden or protected visibility, or if it is static or local, then // has hidden or protected visibility, or if it is static or local, then
// we don't need to use the PLT - we can directly call it. // we don't need to use the PLT - we can directly call it.
if (Subtarget->isTargetELF() && if (Subtarget->isTargetELF() &&
getTargetMachine().getRelocationModel() == Reloc::PIC_ && DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
OpFlags = X86II::MO_PLT; OpFlags = X86II::MO_PLT;
} else if (Subtarget->isPICStyleStubAny() && } else if (Subtarget->isPICStyleStubAny() &&
@ -2913,7 +2913,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// On ELF targets, in either X86-64 or X86-32 mode, direct calls to // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
// external symbols should go through the PLT. // external symbols should go through the PLT.
if (Subtarget->isTargetELF() && if (Subtarget->isTargetELF() &&
getTargetMachine().getRelocationModel() == Reloc::PIC_) { DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
OpFlags = X86II::MO_PLT; OpFlags = X86II::MO_PLT;
} else if (Subtarget->isPICStyleStubAny() && } else if (Subtarget->isPICStyleStubAny() &&
(!Subtarget->getTargetTriple().isMacOSX() || (!Subtarget->getTargetTriple().isMacOSX() ||
@ -2952,7 +2952,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
RegsToPass[i].second.getValueType())); RegsToPass[i].second.getValueType()));
// Add a register mask operand representing the call-preserved registers. // Add a register mask operand representing the call-preserved registers.
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
assert(Mask && "Missing call preserved mask for calling convention"); assert(Mask && "Missing call preserved mask for calling convention");
Ops.push_back(DAG.getRegisterMask(Mask)); Ops.push_back(DAG.getRegisterMask(Mask));
@ -2976,7 +2976,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Create the CALLSEQ_END node. // Create the CALLSEQ_END node.
unsigned NumBytesForCalleeToPop; unsigned NumBytesForCalleeToPop;
if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
getTargetMachine().Options.GuaranteedTailCallOpt)) DAG.getTarget().Options.GuaranteedTailCallOpt))
NumBytesForCalleeToPop = NumBytes; // Callee pops everything NumBytesForCalleeToPop = NumBytes; // Callee pops everything
else if (!Is64Bit && !IsTailCallConvention(CallConv) && else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
!Subtarget->getTargetTriple().isOSMSVCRT() && !Subtarget->getTargetTriple().isOSMSVCRT() &&
@ -3147,7 +3147,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC); bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC); bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
if (getTargetMachine().Options.GuaranteedTailCallOpt) { if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
if (IsTailCallConvention(CalleeCC) && CCMatch) if (IsTailCallConvention(CalleeCC) && CCMatch)
return true; return true;
return false; return false;
@ -3159,7 +3159,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
// Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
// emit a special epilogue. // emit a special epilogue.
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
if (RegInfo->needsStackRealignment(MF)) if (RegInfo->needsStackRealignment(MF))
return false; return false;
@ -3188,7 +3188,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
getTargetMachine(), ArgLocs, *DAG.getContext()); DAG.getTarget(), ArgLocs, *DAG.getContext());
CCInfo.AnalyzeCallOperands(Outs, CC_X86); CCInfo.AnalyzeCallOperands(Outs, CC_X86);
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
@ -3209,7 +3209,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
if (Unused) { if (Unused) {
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
getTargetMachine(), RVLocs, *DAG.getContext()); DAG.getTarget(), RVLocs, *DAG.getContext());
CCInfo.AnalyzeCallResult(Ins, RetCC_X86); CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
CCValAssign &VA = RVLocs[i]; CCValAssign &VA = RVLocs[i];
@ -3223,12 +3223,12 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
if (!CCMatch) { if (!CCMatch) {
SmallVector<CCValAssign, 16> RVLocs1; SmallVector<CCValAssign, 16> RVLocs1;
CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
getTargetMachine(), RVLocs1, *DAG.getContext()); DAG.getTarget(), RVLocs1, *DAG.getContext());
CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
SmallVector<CCValAssign, 16> RVLocs2; SmallVector<CCValAssign, 16> RVLocs2;
CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
getTargetMachine(), RVLocs2, *DAG.getContext()); DAG.getTarget(), RVLocs2, *DAG.getContext());
CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
if (RVLocs1.size() != RVLocs2.size()) if (RVLocs1.size() != RVLocs2.size())
@ -3255,7 +3255,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
// argument is passed on the stack. // argument is passed on the stack.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
getTargetMachine(), ArgLocs, *DAG.getContext()); DAG.getTarget(), ArgLocs, *DAG.getContext());
// Allocate shadow area for Win64 // Allocate shadow area for Win64
if (IsCalleeWin64) if (IsCalleeWin64)
@ -3272,7 +3272,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
const MachineRegisterInfo *MRI = &MF.getRegInfo(); const MachineRegisterInfo *MRI = &MF.getRegInfo();
const X86InstrInfo *TII = const X86InstrInfo *TII =
((const X86TargetMachine&)getTargetMachine()).getInstrInfo(); static_cast<const X86InstrInfo *>(DAG.getTarget().getInstrInfo());
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i]; CCValAssign &VA = ArgLocs[i];
SDValue Arg = OutVals[i]; SDValue Arg = OutVals[i];
@ -3295,12 +3295,12 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
if (!Subtarget->is64Bit() && if (!Subtarget->is64Bit() &&
((!isa<GlobalAddressSDNode>(Callee) && ((!isa<GlobalAddressSDNode>(Callee) &&
!isa<ExternalSymbolSDNode>(Callee)) || !isa<ExternalSymbolSDNode>(Callee)) ||
getTargetMachine().getRelocationModel() == Reloc::PIC_)) { DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
unsigned NumInRegs = 0; unsigned NumInRegs = 0;
// In PIC we need an extra register to formulate the address computation // In PIC we need an extra register to formulate the address computation
// for the callee. // for the callee.
unsigned MaxInRegs = unsigned MaxInRegs =
(getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3; (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i]; CCValAssign &VA = ArgLocs[i];
@ -3424,7 +3424,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
int ReturnAddrIndex = FuncInfo->getRAIndex(); int ReturnAddrIndex = FuncInfo->getRAIndex();
@ -8665,7 +8665,7 @@ X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
// global base reg. // global base reg.
unsigned char OpFlag = 0; unsigned char OpFlag = 0;
unsigned WrapperKind = X86ISD::Wrapper; unsigned WrapperKind = X86ISD::Wrapper;
CodeModel::Model M = getTargetMachine().getCodeModel(); CodeModel::Model M = DAG.getTarget().getCodeModel();
if (Subtarget->isPICStyleRIPRel() && if (Subtarget->isPICStyleRIPRel() &&
(M == CodeModel::Small || M == CodeModel::Kernel)) (M == CodeModel::Small || M == CodeModel::Kernel))
@ -8698,7 +8698,7 @@ SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
// global base reg. // global base reg.
unsigned char OpFlag = 0; unsigned char OpFlag = 0;
unsigned WrapperKind = X86ISD::Wrapper; unsigned WrapperKind = X86ISD::Wrapper;
CodeModel::Model M = getTargetMachine().getCodeModel(); CodeModel::Model M = DAG.getTarget().getCodeModel();
if (Subtarget->isPICStyleRIPRel() && if (Subtarget->isPICStyleRIPRel() &&
(M == CodeModel::Small || M == CodeModel::Kernel)) (M == CodeModel::Small || M == CodeModel::Kernel))
@ -8731,7 +8731,7 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
// global base reg. // global base reg.
unsigned char OpFlag = 0; unsigned char OpFlag = 0;
unsigned WrapperKind = X86ISD::Wrapper; unsigned WrapperKind = X86ISD::Wrapper;
CodeModel::Model M = getTargetMachine().getCodeModel(); CodeModel::Model M = DAG.getTarget().getCodeModel();
if (Subtarget->isPICStyleRIPRel() && if (Subtarget->isPICStyleRIPRel() &&
(M == CodeModel::Small || M == CodeModel::Kernel)) { (M == CodeModel::Small || M == CodeModel::Kernel)) {
@ -8752,7 +8752,7 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset. // With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
!Subtarget->is64Bit()) { !Subtarget->is64Bit()) {
Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
DAG.getNode(X86ISD::GlobalBaseReg, DAG.getNode(X86ISD::GlobalBaseReg,
@ -8774,7 +8774,7 @@ X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
// Create the TargetBlockAddressAddress node. // Create the TargetBlockAddressAddress node.
unsigned char OpFlags = unsigned char OpFlags =
Subtarget->ClassifyBlockAddressReference(); Subtarget->ClassifyBlockAddressReference();
CodeModel::Model M = getTargetMachine().getCodeModel(); CodeModel::Model M = DAG.getTarget().getCodeModel();
const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset(); int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
SDLoc dl(Op); SDLoc dl(Op);
@ -8803,8 +8803,8 @@ X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
// Create the TargetGlobalAddress node, folding in the constant // Create the TargetGlobalAddress node, folding in the constant
// offset if it is legal. // offset if it is legal.
unsigned char OpFlags = unsigned char OpFlags =
Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
CodeModel::Model M = getTargetMachine().getCodeModel(); CodeModel::Model M = DAG.getTarget().getCodeModel();
SDValue Result; SDValue Result;
if (OpFlags == X86II::MO_NO_FLAG && if (OpFlags == X86II::MO_NO_FLAG &&
X86::isOffsetSuitableForCodeModel(Offset, M)) { X86::isOffsetSuitableForCodeModel(Offset, M)) {
@ -9003,7 +9003,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
const GlobalValue *GV = GA->getGlobal(); const GlobalValue *GV = GA->getGlobal();
if (Subtarget->isTargetELF()) { if (Subtarget->isTargetELF()) {
TLSModel::Model model = getTargetMachine().getTLSModel(GV); TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
switch (model) { switch (model) {
case TLSModel::GeneralDynamic: case TLSModel::GeneralDynamic:
@ -9015,9 +9015,9 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
Subtarget->is64Bit()); Subtarget->is64Bit());
case TLSModel::InitialExec: case TLSModel::InitialExec:
case TLSModel::LocalExec: case TLSModel::LocalExec:
return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, return LowerToTLSExecModel(
Subtarget->is64Bit(), GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
getTargetMachine().getRelocationModel() == Reloc::PIC_); DAG.getTarget().getRelocationModel() == Reloc::PIC_);
} }
llvm_unreachable("Unknown TLS model."); llvm_unreachable("Unknown TLS model.");
} }
@ -9030,8 +9030,8 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
// In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
// global base reg. // global base reg.
bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
!Subtarget->is64Bit(); !Subtarget->is64Bit();
if (PIC32) if (PIC32)
OpFlag = X86II::MO_TLVP_PIC_BASE; OpFlag = X86II::MO_TLVP_PIC_BASE;
else else
@ -11666,7 +11666,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
Chain = SP.getValue(1); Chain = SP.getValue(1);
unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); const TargetFrameLowering &TFI = *DAG.getTarget().getFrameLowering();
unsigned StackAlign = TFI.getStackAlignment(); unsigned StackAlign = TFI.getStackAlignment();
Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
if (Align > StackAlign) if (Align > StackAlign)
@ -11725,7 +11725,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
unsigned SPReg = RegInfo->getStackRegister(); unsigned SPReg = RegInfo->getStackRegister();
SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy); SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
Chain = SP.getValue(1); Chain = SP.getValue(1);
@ -11834,7 +11834,7 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
if (ArgMode == 2) { if (ArgMode == 2) {
// Sanity Check: Make sure using fp_offset makes sense. // Sanity Check: Make sure using fp_offset makes sense.
assert(!getTargetMachine().Options.UseSoftFloat && assert(!DAG.getTarget().Options.UseSoftFloat &&
!(DAG.getMachineFunction() !(DAG.getMachineFunction()
.getFunction()->getAttributes() .getFunction()->getAttributes()
.hasAttribute(AttributeSet::FunctionIndex, .hasAttribute(AttributeSet::FunctionIndex,
@ -13026,7 +13026,7 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
if (Depth > 0) { if (Depth > 0) {
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT); SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(ISD::ADD, dl, PtrVT,
@ -13048,7 +13048,7 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op); // FIXME probably not meaningful SDLoc dl(Op); // FIXME probably not meaningful
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction()); unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
assert(((FrameReg == X86::RBP && VT == MVT::i64) || assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
(FrameReg == X86::EBP && VT == MVT::i32)) && (FrameReg == X86::EBP && VT == MVT::i32)) &&
@ -13077,7 +13077,7 @@ unsigned X86TargetLowering::getRegisterByName(const char* RegName,
SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize()); return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
} }
@ -13089,7 +13089,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
EVT PtrVT = getPointerTy(); EVT PtrVT = getPointerTy();
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction()); unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) || assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
(FrameReg == X86::EBP && PtrVT == MVT::i32)) && (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
@ -13136,7 +13136,7 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
SDLoc dl (Op); SDLoc dl (Op);
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); const TargetRegisterInfo* TRI = DAG.getTarget().getRegisterInfo();
if (Subtarget->is64Bit()) { if (Subtarget->is64Bit()) {
SDValue OutChains[6]; SDValue OutChains[6];
@ -15552,10 +15552,10 @@ static unsigned getPseudoCMOVOpc(EVT VT) {
MachineBasicBlock * MachineBasicBlock *
X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI, X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
MachineBasicBlock *MBB) const { MachineBasicBlock *MBB) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); MachineFunction *MF = MBB->getParent();
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
MachineFunction *MF = MBB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const BasicBlock *BB = MBB->getBasicBlock(); const BasicBlock *BB = MBB->getBasicBlock();
@ -15713,7 +15713,7 @@ X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
.addReg(t4); .addReg(t4);
} else { } else {
// Promote i8 to i32 to use CMOV32 // Promote i8 to i32 to use CMOV32
const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
const TargetRegisterClass *RC32 = const TargetRegisterClass *RC32 =
TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit); TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
unsigned SrcReg32 = MRI.createVirtualRegister(RC32); unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
@ -15825,10 +15825,10 @@ X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
MachineBasicBlock * MachineBasicBlock *
X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI, X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
MachineBasicBlock *MBB) const { MachineBasicBlock *MBB) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); MachineFunction *MF = MBB->getParent();
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
MachineFunction *MF = MBB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const BasicBlock *BB = MBB->getBasicBlock(); const BasicBlock *BB = MBB->getBasicBlock();
@ -16222,7 +16222,7 @@ X86TargetLowering::EmitVAARG64WithCustomInserter(
MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
// Machine Information // Machine Information
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
@ -16478,7 +16478,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
XMMSaveMBB->addSuccessor(EndMBB); XMMSaveMBB->addSuccessor(EndMBB);
// Now add the instructions. // Now add the instructions.
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
unsigned CountReg = MI->getOperand(0).getReg(); unsigned CountReg = MI->getOperand(0).getReg();
@ -16561,7 +16561,7 @@ static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
MachineBasicBlock * MachineBasicBlock *
X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
MachineBasicBlock *BB) const { MachineBasicBlock *BB) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
// To "insert" a SELECT_CC instruction, we actually have to insert the // To "insert" a SELECT_CC instruction, we actually have to insert the
@ -16587,7 +16587,7 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
// If the EFLAGS register isn't dead in the terminator, then claim that it's // If the EFLAGS register isn't dead in the terminator, then claim that it's
// live into the sink and copy blocks. // live into the sink and copy blocks.
const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); const TargetRegisterInfo* TRI = BB->getParent()->getTarget().getRegisterInfo();
if (!MI->killsRegister(X86::EFLAGS) && if (!MI->killsRegister(X86::EFLAGS) &&
!checkAndUpdateEFLAGSKill(MI, BB, TRI)) { !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
copy0MBB->addLiveIn(X86::EFLAGS); copy0MBB->addLiveIn(X86::EFLAGS);
@ -16628,9 +16628,9 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
MachineBasicBlock * MachineBasicBlock *
X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
bool Is64Bit) const { bool Is64Bit) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc DL = MI->getDebugLoc();
MachineFunction *MF = BB->getParent(); MachineFunction *MF = BB->getParent();
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
DebugLoc DL = MI->getDebugLoc();
const BasicBlock *LLVM_BB = BB->getBasicBlock(); const BasicBlock *LLVM_BB = BB->getBasicBlock();
assert(MF->shouldSplitStack()); assert(MF->shouldSplitStack());
@ -16700,7 +16700,7 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
// Calls into a routine in libgcc to allocate more space from the heap. // Calls into a routine in libgcc to allocate more space from the heap.
const uint32_t *RegMask = const uint32_t *RegMask =
getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); MF->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
if (Is64Bit) { if (Is64Bit) {
BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
.addReg(sizeVReg); .addReg(sizeVReg);
@ -16748,8 +16748,8 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
MachineBasicBlock * MachineBasicBlock *
X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
MachineBasicBlock *BB) const { MachineBasicBlock *BB) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
assert(!Subtarget->isTargetMacho()); assert(!Subtarget->isTargetMacho());
@ -16805,10 +16805,10 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
// our load from the relocation, sticking it in either RDI (x86-64) // our load from the relocation, sticking it in either RDI (x86-64)
// or EAX and doing an indirect call. The return value will then // or EAX and doing an indirect call. The return value will then
// be in the normal return register. // be in the normal return register.
const X86InstrInfo *TII
= static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
DebugLoc DL = MI->getDebugLoc();
MachineFunction *F = BB->getParent(); MachineFunction *F = BB->getParent();
const X86InstrInfo *TII
= static_cast<const X86InstrInfo*>(F->getTarget().getInstrInfo());
DebugLoc DL = MI->getDebugLoc();
assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
assert(MI->getOperand(3).isGlobal() && "This should be a global"); assert(MI->getOperand(3).isGlobal() && "This should be a global");
@ -16817,7 +16817,7 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
// FIXME: The 32-bit calls have non-standard calling conventions. Use a // FIXME: The 32-bit calls have non-standard calling conventions. Use a
// proper register mask. // proper register mask.
const uint32_t *RegMask = const uint32_t *RegMask =
getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); F->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
if (Subtarget->is64Bit()) { if (Subtarget->is64Bit()) {
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
TII->get(X86::MOV64rm), X86::RDI) TII->get(X86::MOV64rm), X86::RDI)
@ -16829,7 +16829,7 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
addDirectMem(MIB, X86::RDI); addDirectMem(MIB, X86::RDI);
MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
} else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
TII->get(X86::MOV32rm), X86::EAX) TII->get(X86::MOV32rm), X86::EAX)
.addReg(0) .addReg(0)
@ -16861,9 +16861,8 @@ MachineBasicBlock *
X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
MachineBasicBlock *MBB) const { MachineBasicBlock *MBB) const {
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
MachineFunction *MF = MBB->getParent(); MachineFunction *MF = MBB->getParent();
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const BasicBlock *BB = MBB->getBasicBlock(); const BasicBlock *BB = MBB->getBasicBlock();
@ -16925,8 +16924,8 @@ X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
unsigned PtrStoreOpc = 0; unsigned PtrStoreOpc = 0;
unsigned LabelReg = 0; unsigned LabelReg = 0;
const int64_t LabelOffset = 1 * PVT.getStoreSize(); const int64_t LabelOffset = 1 * PVT.getStoreSize();
Reloc::Model RM = getTargetMachine().getRelocationModel(); Reloc::Model RM = MF->getTarget().getRelocationModel();
bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) && bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
(RM == Reloc::Static || RM == Reloc::DynamicNoPIC); (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
// Prepare IP either in reg or imm. // Prepare IP either in reg or imm.
@ -16970,7 +16969,7 @@ X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
.addMBB(restoreMBB); .addMBB(restoreMBB);
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
MIB.addRegMask(RegInfo->getNoPreservedMask()); MIB.addRegMask(RegInfo->getNoPreservedMask());
thisMBB->addSuccessor(mainMBB); thisMBB->addSuccessor(mainMBB);
thisMBB->addSuccessor(restoreMBB); thisMBB->addSuccessor(restoreMBB);
@ -16999,9 +16998,8 @@ MachineBasicBlock *
X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
MachineBasicBlock *MBB) const { MachineBasicBlock *MBB) const {
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
MachineFunction *MF = MBB->getParent(); MachineFunction *MF = MBB->getParent();
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
// Memory Reference // Memory Reference
@ -17017,7 +17015,7 @@ X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
unsigned Tmp = MRI.createVirtualRegister(RC); unsigned Tmp = MRI.createVirtualRegister(RC);
// Since FP is only updated here but NOT referenced, it's treated as GPR. // Since FP is only updated here but NOT referenced, it's treated as GPR.
const X86RegisterInfo *RegInfo = const X86RegisterInfo *RegInfo =
static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo()); static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP; unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
unsigned SP = RegInfo->getStackRegister(); unsigned SP = RegInfo->getStackRegister();
@ -17192,12 +17190,12 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case X86::FP80_TO_INT16_IN_MEM: case X86::FP80_TO_INT16_IN_MEM:
case X86::FP80_TO_INT32_IN_MEM: case X86::FP80_TO_INT32_IN_MEM:
case X86::FP80_TO_INT64_IN_MEM: { case X86::FP80_TO_INT64_IN_MEM: {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); MachineFunction *F = BB->getParent();
const TargetInstrInfo *TII = F->getTarget().getInstrInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
// Change the floating point control register to use "round towards zero" // Change the floating point control register to use "round towards zero"
// mode when truncating to an integer value. // mode when truncating to an integer value.
MachineFunction *F = BB->getParent();
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
addFrameReference(BuildMI(*BB, MI, DL, addFrameReference(BuildMI(*BB, MI, DL,
TII->get(X86::FNSTCW16m)), CWFrameIdx); TII->get(X86::FNSTCW16m)), CWFrameIdx);
@ -17277,7 +17275,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case X86::VPCMPESTRM128MEM: case X86::VPCMPESTRM128MEM:
assert(Subtarget->hasSSE42() && assert(Subtarget->hasSSE42() &&
"Target must have SSE4.2 or AVX features enabled"); "Target must have SSE4.2 or AVX features enabled");
return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo()); return EmitPCMPSTRM(MI, BB, BB->getParent()->getTarget().getInstrInfo());
// String/text processing lowering. // String/text processing lowering.
case X86::PCMPISTRIREG: case X86::PCMPISTRIREG:
@ -17290,15 +17288,15 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case X86::VPCMPESTRIMEM: case X86::VPCMPESTRIMEM:
assert(Subtarget->hasSSE42() && assert(Subtarget->hasSSE42() &&
"Target must have SSE4.2 or AVX features enabled"); "Target must have SSE4.2 or AVX features enabled");
return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo()); return EmitPCMPSTRI(MI, BB, BB->getParent()->getTarget().getInstrInfo());
// Thread synchronization. // Thread synchronization.
case X86::MONITOR: case X86::MONITOR:
return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget); return EmitMonitor(MI, BB, BB->getParent()->getTarget().getInstrInfo(), Subtarget);
// xbegin // xbegin
case X86::XBEGIN: case X86::XBEGIN:
return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo()); return EmitXBegin(MI, BB, BB->getParent()->getTarget().getInstrInfo());
// Atomic Lowering. // Atomic Lowering.
case X86::ATOMAND8: case X86::ATOMAND8:
@ -21354,8 +21352,8 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
const GlobalValue *GV = GA->getGlobal(); const GlobalValue *GV = GA->getGlobal();
// If we require an extra load to get this address, as in PIC mode, we // If we require an extra load to get this address, as in PIC mode, we
// can't accept it. // can't accept it.
if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, if (isGlobalStubReference(
getTargetMachine()))) Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
return; return;
Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),