RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
Code Issues Projects Releases Wiki Activity

Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended.

Browse Source 
llvm-svn: 157122
This commit is contained in:
Craig Topper 2012-05-19 19:14:18 +00:00
parent ebbaac4318
commit 55b5aa4042
2 changed files with 28 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -1038,7 +1038,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SrcRegNum = CurOp + X86::AddrNumOperands;
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
SrcRegNum++;
++SrcRegNum;
EmitMemModRMByte(MI, CurOp,
GetX86RegNum(MI.getOperand(SrcRegNum)),
@ -1051,15 +1051,15 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SrcRegNum = CurOp + 1;
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
SrcRegNum++;
++SrcRegNum;
if(HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
SrcRegNum++;
if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
++SrcRegNum;
EmitRegModRMByte(MI.getOperand(SrcRegNum),
GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
// 2 operands skipped with HasMemOp4, comensate accordingly
// 2 operands skipped with HasMemOp4, compensate accordingly
CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
if (HasVEX_4VOp3)
++CurOp;
@ -1072,7 +1072,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
++AddrOperands;
++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
}
if(HasMemOp4) // Skip second register source (encoded in I8IMM)
if (HasMemOp4) // Skip second register source (encoded in I8IMM)
++FirstMemOp;
EmitByte(BaseOpcode, CurByte, OS);
@ -1090,7 +1090,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
case X86II::MRM4r: case X86II::MRM5r:
case X86II::MRM6r: case X86II::MRM7r:
if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
CurOp++;
++CurOp;
EmitByte(BaseOpcode, CurByte, OS);
EmitRegModRMByte(MI.getOperand(CurOp++),
(TSFlags & X86II::FormMask)-X86II::MRM0r,
@ -1101,7 +1101,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
case X86II::MRM4m: case X86II::MRM5m:
case X86II::MRM6m: case X86II::MRM7m:
if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
CurOp++;
++CurOp;
EmitByte(BaseOpcode, CurByte, OS);
EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
TSFlags, CurByte, OS, Fixups);
@ -1156,16 +1156,16 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
// in bits[7:4] of a immediate byte.
if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
: CurOp);
CurOp++;
bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg());
unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
RegNum |= GetX86RegNum(MO) << 4;
: CurOp);
++CurOp;
unsigned RegNum = GetX86RegNum(MO) << 4;
if (X86II::isX86_64ExtendedReg(MO.getReg()))
RegNum |= 1 << 7;
// If there is an additional 5th operand it must be an immediate, which
// is encoded in bits[3:0]
if(CurOp != NumOps) {
if (CurOp != NumOps) {
const MCOperand &MIMM = MI.getOperand(CurOp++);
if(MIMM.isImm()) {
if (MIMM.isImm()) {
unsigned Val = MIMM.getImm();
assert(Val < 16 && "Immediate operand value out of range");
RegNum |= Val;

26
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -1289,14 +1289,14 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
unsigned SrcRegNum = CurOp+1;
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
SrcRegNum++;
++SrcRegNum;
if(HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
SrcRegNum++;
if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
++SrcRegNum;
emitRegModRMByte(MI.getOperand(SrcRegNum).getReg(),
X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
// 2 operands skipped with HasMemOp4, comensate accordingly
// 2 operands skipped with HasMemOp4, compensate accordingly
CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
if (HasVEX_4VOp3)
++CurOp;
@ -1309,7 +1309,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
++AddrOperands;
++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
}
if(HasMemOp4) // Skip second register source (encoded in I8IMM)
if (HasMemOp4) // Skip second register source (encoded in I8IMM)
++FirstMemOp;
MCE.emitByte(BaseOpcode);
@ -1329,7 +1329,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRM4r: case X86II::MRM5r:
case X86II::MRM6r: case X86II::MRM7r: {
if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
CurOp++;
++CurOp;
MCE.emitByte(BaseOpcode);
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
(Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
@ -1366,7 +1366,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRM4m: case X86II::MRM5m:
case X86II::MRM6m: case X86II::MRM7m: {
if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
CurOp++;
++CurOp;
intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ?
(MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ?
X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
@ -1439,15 +1439,15 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
const MachineOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
: CurOp);
CurOp++;
bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg());
unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
RegNum |= X86_MC::getX86RegNum(MO.getReg()) << 4;
++CurOp;
unsigned RegNum = X86_MC::getX86RegNum(MO.getReg()) << 4;
if (X86II::isX86_64ExtendedReg(MO.getReg()))
RegNum |= 1 << 7;
// If there is an additional 5th operand it must be an immediate, which
// is encoded in bits[3:0]
if(CurOp != NumOps) {
if (CurOp != NumOps) {
const MachineOperand &MIMM = MI.getOperand(CurOp++);
if(MIMM.isImm()) {
if (MIMM.isImm()) {
unsigned Val = MIMM.getImm();
assert(Val < 16 && "Immediate operand value out of range");
RegNum |= Val;